# US 2014/0151741 A1 · Semiconductor Construction, Semiconductor Unit, and Manufacturing Method Thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151741 A1 - Document ID: US20140151741A1 - Status: Published application - Kind: A1 - Application number: 13/835,632 - Filed: 2013-03-15 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Unistars Corporation - Applicants: Unistars - Inventors: Tien-hao Huang; Shang-Yi Wu; Yi-chun Wu - Web page: https://patentgrep.com/patent/US20140151741A1 ## CPC - H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls - H10H 20/036: {of packages} - H10H 20/8506: {Containers} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor structure and its manufacturing method including multiple steps are provided. First, a patterned circuit board having a substrate and a patterned circuit layer is provided. The substrate includes a first surface, a second surface, at least one connecting channel, and at least one conductive through hole, wherein patterned circuit layer is disposed on the first surface, a second surface, and the inside wall of the conductive through hole. Then, the patterned circuit board is disposed on a carrier, and the patterned circuit layer disposed on one of the first surface and the second surface is touched with the carrier. Then, a filling process is applied. A filling material flows to the conductive through hole via the first surface or the second surface from the connecting channel. Then, a package material is provided to produce a semiconductor structure. ## Claims ### Claim 1 A semiconductor structure, comprising: a substrate having a first surface, a second surface, at least one through hole, and at least one connecting channel; a patterned circuit layer disposed on the first surface, the second surface, and in each of the through holes, wherein the patterned circuit layer in the through hole is electrically connected to the patterned circuit layers on the first and second surfaces; at least one chip bonded on the substrate and electrically connected to the patterned circuit layer; a insulating filling material having a first part, a second part, and a third part, wherein the first part fills the through hole, the third part fills all of the connecting channels, and the second part connects the first and the third parts; and a packaging material covering each of the chips and a part of the substrate. ### Claim 2 (depends on 1) The semiconductor structure as in claim 1, wherein the substrate is a metal substrate. ### Claim 3 (depends on 2) The semiconductor structure as in claim 2, further comprising an insulating layer wherein the insulating layer is disposed on the first surface, the second surface, and the inner wall of each through hole, and the patterned circuit layer is disposed on the insulating layer. ### Claim 4 (depends on 1) The semiconductor structure as in claim 1, wherein the chip is a light-emitted diode (LED) and the chip packaging material is a transparent glue. ### Claim 5 (depends on 1) The semiconductor structure as in claim 1, wherein the through hole is adjacent to the connecting channel, the second part is located on the portion of the second surface between the through hole and the connecting channel when a part of the patterned circuit layer is disposed on the portion of the first surface between the through hole and the connecting channel, and the second part is located on the portion of the first surface between the through hole and the connecting channel when a part of the patterned circuit layer is disposed on the portion of the second surface between the through hole and the connecting channel,. ### Claim 6 (depends on 1) The semiconductor structure as in claim 1, wherein the surface of the second part of filling material is higher than the top of the first or second surface and is lower than or equal to the top of the patterned circuit layer corresponding to the first or second surface. ### Claim 7 A semiconductor unit, comprising: a substrate having a first surface, a second surface, and at least one through hole; a patterned circuit layer disposed on the first surface, the second surface, and in all of the through holes, wherein the patterned circuit layer in the through hole is electrically connected to the patterned circuit layer on the first surface and the patterned circuit layer on the second surfaces; at least one chip disposed on the substrate and electrically connected to the patterned circuit layer; a filling material having a first part, a second part, and a third part, wherein the first part fills the through hole, the third part is located on the side of the substrate adjacent to the through hole, and the second part connects the first and the third parts; and a packaging material covering each of the chips and a part of the substrate. ### Claim 8 (depends on 7) The semiconductor unit as in claim 7, wherein the substrate is a metal substrate. ### Claim 9 (depends on 8) The semiconductor unit as in claim 8, wherein an insulating layer is further disposed on the first surface, the second surface, and the inner wall of each through hole, and the patterned circuit layer is disposed on the insulating layer. ### Claim 10 (depends on 7) The semiconductor unit as in claim 7, wherein the chip packaging material is a transparent glue and the chip is a light-emitted diode. ### Claim 11 (depends on 7) The semiconductor unit as in claim 7, wherein when a part of the patterned circuit layer is disposed on the portion of the first surface between the through hole and the side of the substrate, the second part is located on the portion of the second surface between the through hole and the side of the substrate; when a part of the patterned circuit layer is disposed on the portion of the second surface between the through hole and the side of the substrate, the second part is located on the portion of the first surface between the through hole and the side of the substrate. ### Claim 12 (depends on 7) The semiconductor unit as in claim 7, wherein the surface of the second part is higher than the top of the first or second surface, and is lower than or equal to the top of the patterned circuit layer corresponding to the first or second surface. ### Claim 13 A manufacturing method of a semiconductor structure, comprising: providing a substrate having a first surface in one side, a second surface in the reversed side, and at least one connecting channel; structuring at least one through hole in the substrate; forming an insulating layer on the first surface, the second surface, and the inner wall of each through hole; developing a patterned circuit layer on the insulating layer, wherein the patterned circuit layer is disposed on the first surface, the second surface, and in each of the through hole, the patterned circuit layer in the through hole is electrically connected to the patterned circuit layer on the first surface and the patterned circuit layer on the second surfaces; disposing the patterned circuit board on a carrier, wherein the patterned circuit layer on the first or second surface touches the carrier; implementing a filling process in the connecting channel, wherein a filling material is an insulating material and flows to the through hole from the connecting channel via the first or second surface, and then the filing material is cured; providing at least one chip, wherein each of the chips is electrically connected to the corresponding patterned circuit layer; and providing a packaging material covering each of the chips and a part of the substrate to form a semiconductor structure. ### Claim 14 (depends on 13) The manufacturing method of a semiconductor structure as in claim 13, wherein the substrate is a metal substrate. ### Claim 15 (depends on 14) The manufacturing method of a semiconductor structure as in claim 14, wherein a part of or the entire connecting channel is hollowed out and acts as a dicing channel. ### Claim 16 (depends on 13) The manufacturing method of a semiconductor structure as in claim 13, wherein the chip packaging material is a transparent glue and the chip is a light-emitted diode. ### Claim 17 (depends on 13) The manufacturing method of a semiconductor structure as in claim 13, after the filling process is completed, the manufacturing method further comprises: removing the carrier. ### Claim 18 (depends on 13) The manufacturing method of a semiconductor structure as in claim 13, wherein after the semiconductor structure is formed, the manufacturing method further comprises: cutting the connecting channel to form a plurality of semiconductor units. ### Claim 19 (depends on 13) The manufacturing method of a semiconductor structure as in claim 13, the filling material has a first part, a second part, and a third part, wherein the first part fills each of the through holes, the third part fills each of the connecting channels, and the second part connects the first and the third parts. ### Claim 20 (depends on 19) The manufacturing method of a semiconductor structure as in claim 19, wherein the through hole is adjacent to the connecting channel and when a part of the patterned circuit layer is disposed on the portion of the first surface between the through hole and the connecting channel, the second part is located on the portion of the second surface between the through hole and the connecting channel; when a part of the patterned circuit layer is disposed on the portion of the second surface between the through hole and the connecting channel, the second part is located on the portion of the first surface between the through hole and the connecting channel. ### Claim 21 (depends on 20) The manufacturing method of a semiconductor structure as in claim 20, wherein when a part of the patterned circuit layer between the through hole and the connecting channel is disposed on the second surface, and the patterned circuit board is disposed on the carrier so that the first surface faces toward the carrier, a flow channel exists between the first surface and the carrier, the filling material flows between the connecting channel and the through hole via the flow channel, and the second part is formed in the flow channel. ### Claim 22 (depends on 21) The manufacturing method of a semiconductor structure as in claim 21, wherein the filling material fills the through hole in a direction away from the carrier. ### Claim 23 (depends on 20) The manufacturing method of a semiconductor structure as in claim 20, wherein when a part of the patterned circuit layer between the through hole and the connecting channel is disposed on the first surface, and the patterned circuit board is disposed on the carrier so that the first surface faces towards the carrier, a part of the patterned circuit layer on the first surface touches the carrier, and after filling up in the space between the connecting channel and the carrier, the filling material flows to the through hole via the second surface, and then the second part is formed on the second surface. ### Claim 24 (depends on 23) The manufacturing method of a semiconductor structure as in claim 23, wherein the filling material fills the through hole in a direction towards the carrier. ### Claim 25 (depends on 13) The manufacturing method of a semiconductor structure as in claim 13, wherein the viscosity coefficient of the filling material is between 400 cps and 4000 cps. ### Claim 26 (depends on 25) The manufacturing method of a semiconductor structure as in claim 25, wherein the viscosity coefficient of the filling material is between 500 cps and 2000 cps. ### Claim 27 (depends on 13) The manufacturing method of a semiconductor structure as in claim 13, wherein the carrier is a tape.