# US 2014/0151724 A1 · Method for Producing an Optoelectronic Semiconductor Component and Such a Semiconductor Component

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- Number: US 2014/0151724 A1
- Document ID: US20140151724A1
- Status: Published application
- Kind: A1
- Application number: 14/122,513
- Filed: 2012-05-14
- Published: 2014-06-05
- Earliest claimed: 2011-06-06
- Assignees: OSRAM Opto Semiconductors GmbH
- Inventors: Siegfried Herrmann
- Web page: https://patentgrep.com/patent/US20140151724A1

## CPC

- H10F 77/70: Surface textures, e.g. pyramid structures
- H10H 20/82: Roughened surfaces, e.g. at the interface between epitaxial layers
- H10H 20/85: Packages
- H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10H 20/036: {of packages}
- H10H 20/0364: {of interconnections}
- H10H 20/8506: {Containers}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/9413: {on encapsulations}
- H10W 90/00: Package configurations
- H10W 90/10: Configurations of laterally-adjacent chips
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for producing a semiconductor component is disclosed. A carrier substrate includes a mounting region and an opening, which is formed in the mounting region of the carrier substrate. After mounting a semiconductor chip, an electrically insulating layer is applied to the carrier substrate in such a way that the electrically insulating layer completely fills the first opening in the carrier substrate. A second opening is formed in the electrically insulating layer. An electrically conductive layer is then applied to the electrically insulating layer in such a way that the second opening is filled with the electrically conductive layer in the form of a via. A semiconductor component produced in this way is also provided.

## Claims

### Claim at position 1

1-15. (canceled)

### Claim 16

A method for producing an optoelectronic semiconductor component, the method comprising:
providing a semiconductor chip that comprises an active layer configured to generate radiation;
providing a carrier substrate that comprises a mounting region for the semiconductor chip and a first opening, which is formed in the mounting region of the carrier substrate;
mounting the semiconductor chip on the mounting region of the carrier substrate;
applying an electrically insulating layer to a side of the carrier substrate remote from the semiconductor chip in such a way that the electrically insulating layer completely fills the first opening in the carrier substrate;
forming a second opening in the electrically insulating layer, the second opening being formed in the region of the first opening in the carrier substrate; and
applying an electrically conductive layer on a side of the electrically insulating layer remote from the carrier substrate in such a way that the electrically conductive layer fills the second opening in the electrically insulating layer in the form of a via.

### Claim 17 (depends on 16)

The method according to claim 16, wherein the semiconductor chip comprises two mutually electrically insulated electrical contact regions on the side remote from the carrier substrate, the first and second openings being formed in a region vertically adjacent the two contact regions.

### Claim 18 (depends on 16)

The method according to claim 16, wherein the diameter of the second opening is smaller than the diameter of the first opening.

### Claim 19 (depends on 18)

The method according to claim 18, wherein the first opening has a diameter of at least 70 μm and at most 90 μm and the second opening has a diameter of at least 10 μm and at most 30 μm.

### Claim 20 (depends on 16)

The method according to claim 16, wherein the second opening is formed at least in part in the first opening.

### Claim 21 (depends on 16)

The method according to claim 16, wherein the via is punctiform.

### Claim 22 (depends on 16)

The method according to claim 16, further comprising patterning the electrically conductive layer.

### Claim 23 (depends on 16)

The method according to claim 16, further comprising roughening an outcoupling face of the semiconductor chip, which is on the opposite side from the carrier substrate, after applying the electrically conductive layer.

### Claim 24 (depends on 16)

The method according to claim 16, further comprising applying a converter layer and/or a passivation layer to the opposite side of the semiconductor chip from the carrier substrate after applying the electrically conductive layer.

### Claim 25 (depends on 16)

The method according to claim 16, further comprising thinning or completely detaching a growth substrate of the semiconductor chip.

### Claim 26 (depends on 16)

The method according to claim 16, wherein:
a plurality of semiconductor chips is provided; and
the carrier substrate comprises a plurality of mounting regions for the semiconductor chips and a plurality of first openings;
each of the semiconductor chips is arranged on a corresponding one of the mounting regions; and
a plurality of second openings is formed in the electrically insulating layer, one of the second openings being formed in the region of a corresponding one of the first openings in the carrier substrate.

### Claim 27 (depends on 26)

The method according to claim 26, further comprising singulating the semiconductor component is singulated into individual semiconductor chips and/or into semiconductor chip modules.

### Claim 28 (depends on 26)

The method according to claim 26, wherein mounting the semiconductor chip comprises applying the semiconductor chips to the mounting regions of the carrier substrate using a pick-and-place method.

### Claim 29

An optoelectronic semiconductor component, comprising:
a semiconductor chip;
a carrier substrate;
wherein the semiconductor chip comprises an active layer configured to generate radiation;
wherein the carrier substrate comprises a mounting region for the semiconductor chip and a first opening, which is formed in the mounting region of the carrier substrate;
wherein the semiconductor chip is arranged on the mounting region of the carrier substrate;
wherein an electrically insulating layer is applied to the side of the carrier substrate remote from the semiconductor chip, the insulating layer filling the first opening in the carrier substrate;
wherein a second opening is formed in the electrically insulating layer in the region of the first opening in the carrier substrate;
wherein an electrically conductive layer is arranged on a side of the electrically insulating layer remote from the carrier substrate, the conductive layer filling the second opening in the electrically insulating layer in the form of a via; and
wherein the mounting region of the carrier substrate is free of the electrically insulating layer and the electrically conductive layer.

### Claim 30 (depends on 29)

The optoelectronic semiconductor component according to claim 29, wherein the side of the carrier substrate facing the semiconductor chip is free of the electrically insulating layer.

### Claim 31 (depends on 29)

The optoelectronic semiconductor component according to claim 29, wherein the carrier substrate comprises a metal foil or a ceramic foil.

### Claim 32 (depends on 29)

The optoelectronic semiconductor component according to claim 29, wherein the electrically insulating layer comprising a plastic layer.

### Claim 33

A method for producing an optoelectronic semiconductor component, the method comprising:
A1) providing a semiconductor chip that comprises an active layer configured to generate radiation;
A2) providing a carrier substrate which comprises a mounting region for the semiconductor chip and a first opening, which is formed in the mounting region of the carrier substrate;
B) mounting the semiconductor chip on the mounting region of the carrier substrate;
C) applying an electrically insulating layer to a side of the carrier substrate remote from the semiconductor chip in such a way that the electrically insulating layer completely fills the first opening in the carrier substrate;
D) forming a second opening in the electrically insulating layer, the second opening being formed in the region of the first opening in the carrier substrate; and
E) applying an electrically conductive layer on a side of the electrically insulating layer remote from the carrier substrate in such a way that the electrically conductive layer fills the second opening in the electrically insulating layer in the form of a via, wherein the method steps B) to E) are performed in the claimed sequence.