# US 2014/0151720 A1 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151720 A1 - Document ID: US20140151720A1 - Status: Published application - Kind: A1 - Application number: 14/025,836 - Filed: 2013-09-13 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: E Ink Holdings Inc. - Applicants: E Ink Holdings Inc. - Inventors: Wei-Chou Lan; Ted-Hong Shinn - Web page: https://patentgrep.com/patent/US20140151720A1 ## CPC - H10D 30/6728: {Vertical TFTs} - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 86/40: characterised by multiple TFTs - H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer} - H10D 86/60: wherein the TFTs are in active matrices - H10H 20/062: {Light-emitting semiconductor devices having field effect type light-emitting regions, e.g. light-emitting High-Electron Mobility Transistors} - H10K 59/1213: {the pixel elements being TFTs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A semiconductor device adapted for being disposed on a substrate is provided. The semiconductor device includes a pixel electrode, a drain, a semiconductor channel layer, a source, a gate insulation layer and a side-gate. The pixel electrode is disposed on the substrate. The drain is disposed on the pixel electrode and exposes a portion of pixel electrode. The semiconductor channel layer is disposed on the drain. The source is disposed on the semiconductor channel layer. The gate insulation layer is disposed on the substrate, at least covers the source and surrounds the semiconductor channel layer. The side-gate is disposed on the gate insulation layer and extendedly covers the substrate along at least one side of the gate insulation layer. An extending direction of a portion of the side-gate is identical to a stacking direction of the drain, the semiconductor channel layer and the source. ## Claims ### Claim 1 A semiconductor device adapted for being disposed on a substrate, comprising: a pixel electrode disposed on the substrate; a drain disposed on the pixel electrode and exposing a portion of the pixel electrode; a semiconductor channel layer disposed on the drain; a source disposed on the semiconductor channel layer; a gate insulation layer disposed on the substrate and at least covering the source and surrounding the semiconductor channel layer; and a side-gate disposed on the gate insulation layer and extendedly covering the substrate along at least one side of the gate insulation layer, wherein an extending direction of a portion of the side-gate is identical to a stacking direction of the drain, the semiconductor channel layer and the source. ### Claim 2 (depends on 1) The semiconductor device as recited in claim 1, further comprising: a sacrifice layer disposed on the drain, wherein the sacrifice layer covers on the semiconductor channel layer, and an upper surface of the sacrifice layer is coplanar with an upper surface of the semiconductor channel layer. ### Claim 3 (depends on 2) The semiconductor device as recited in claim 2, wherein the source is further extendedly disposed on the sacrifice layer. ### Claim 4 (depends on 1) The semiconductor device as recited in claim 1, wherein an orthographic projection area of the source on the substrate is overlapped with and smaller than an orthographic projection area of the drain on the substrate. ### Claim 5 (depends on 1) The semiconductor device as recited in claim 1, wherein the gate insulation layer covers the source and the semiconductor channel layer. ### Claim 6 (depends on 1) The semiconductor device as recited in claim 1, further comprising: a protective layer covering the side-gate, the gate insulation layer, the drain and the portion of the pixel electrode. ### Claim 7 A manufacturing method of a semiconductor device, comprising: forming a pixel electrode and a first metal layer located above the pixel electrode on the substrate; forming a sacrifice material layer to cover the substrate and the first metal layer, wherein the sacrifice material layer has an opening, and a portion of the first metal layer is exposed by the opening; forming a semiconductor material layer in the opening and covering the sacrifice material layer, wherein the semiconductor material layer covers the potion of the first metal layer exposed by the opening, and a portion of the semiconductor material layer located in the opening is defined as a semiconductor channel layer; removing a portion of the semiconductor material layer located on the sacrifice material layer to expose an upper surface of the semiconductor channel layer; forming a source on the upper surface of the semiconductor channel layer; at least removing the sacrifice material layer exposed outside of the source by using the source as an etching mask; forming a gate insulation layer on the substrate, the gate insulation layer at least covering the source and surrounding the semiconductor channel layer; removing the first metal layer exposed outside of the gate insulation layer to expose a portion of the pixel electrode and define a drain; and forming a side-gate on the gate insulation layer, the side-gate extendedly covering the substrate along at least one side of the gate insulation layer, wherein an extending direction of a portion of the side-gate is identical to a stacking direction of the drain, the semiconductor channel layer and the source. ### Claim 8 (depends on 7) The manufacturing method of the semiconductor device as recited in claim 7, wherein the process of forming the semiconductor material layer comprises sol-gel process, chemical vapor deposition or physical vapor deposition. ### Claim 9 (depends on 7) The manufacturing method of the semiconductor device as recited in claim 7, wherein the opening is filled with the semiconductor material layer, and an upper surface of the sacrifice material layer is coplanar with the upper surface of the semiconductor channel layer. ### Claim 10 (depends on 9) The manufacturing method of the semiconductor device as recited in claim 9, wherein the source further extendedly covers the sacrifice material layer while forming the source, and a sacrifice layer is formed to cover the semiconductor channel layer after removing the sacrifice material layer exposed outside of the source. ### Claim 11 (depends on 7) The manufacturing method of the semiconductor device as recited in claim 7, wherein an orthographic projection area of the source on the substrate is overlapped with and smaller than an orthographic projection area of the semiconductor channel layer on the substrate while forming the source, and the portion of the semiconductor material layer is removed while removing the sacrifice material layer exposed outside of the source. ### Claim 12 (depends on 11) The manufacturing method of the semiconductor device as recited in claim 11, wherein the gate insulation layer covers the source and the semiconductor channel layer. ### Claim 13 (depends on 7) The manufacturing method of the semiconductor device as recited in claim 7, wherein a length of the semiconductor channel layer is equal to a thickness of the semiconductor channel layer. ### Claim 14 (depends on 7) The manufacturing method of the semiconductor device as recited in claim 7, wherein an orthographic projection area of the source on the substrate is overlapped with and smaller than an orthographic projection area of the drain on the substrate. ### Claim 15 (depends on 7) The manufacturing method of the semiconductor device as recited in claim 7, further comprising: forming a protective layer to cover the side-gate, the gate insulation layer, the drain and the portion of the pixel electrode after forming the side-gate on the gate insulation layer.