# US 2014/0151712 A1 · Enhancement-mode high electron mobility transistor structure and method of making same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0151712 A1
- Document ID: US20140151712A1
- Status: Published application
- Kind: A1
- Application number: 13/912,834
- Filed: 2013-06-07
- Published: 2014-06-05
- Earliest claimed: 2012-06-07
- Assignees: Iqe Kc, LLC
- Applicants: Iqe, Kc, LLC
- Inventors: Yu Cao; Oleg Laboutin; Wayne Johnson
- Web page: https://patentgrep.com/patent/US20140151712A1

## CPC

- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4732: {using Group III-V semiconductor material}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An epitaxial structure, such as an enhancement-mode high electron mobility transistor (HEMT) includes a first barrier layer over an aluminum gallium nitride channel layer. The first barrier layer is formed at a first temperature and is overlaid by a second barrier layer formed at a second temperature that is lower than that of the first temperature. The first barrier layer acts as an etch stop when forming a gate recess in the second barrier layer by a wet or dry etching.

## Claims

### Claim 1

An epitaxial structure, comprising:
a) a substrate;
b) a buffer layer on the substrate, the buffer layer including gallium nitride;
c) a channel layer over the buffer layer, the channel layer consisting essentially of InxGa1-xN, where 0≦x≦1, and wherein the channel layer includes a 2-dimensional electron gas region distal to the buffer layer;
d) a first AlN barrier layer over the channel layer formed at a first temperature; and
e) a second AlN barrier layer on the first barrier layer, the second barrier being formed at a second temperature, the second temperature being lower than the first temperature, at which the first barrier layer is formed.

### Claim 2 (depends on 1)

The epitaxial structure of claim 1, wherein the 2-dimensional electron gas region is distal to the buffer layer.

### Claim 3 (depends on 2)

The epitaxial structure of claim 2, wherein the first barrier layer is formed at a temperature in a range of between about 900° C. and about 1,300° C.

### Claim 4 (depends on 3)

The epitaxial structure of claim 3, wherein the second barrier layer is formed at a temperature in a range of between about 300° C. and about 800° C.

### Claim 5 (depends on 4)

The epitaxial structure of claim 4, wherein the first barrier layer has a thickness in a range of between about 0.5 nm and about 2.0 nm.

### Claim 6 (depends on 5)

The epitaxial structure of claim 5, wherein the second barrier layer has a thickness in a range of between about 1.0 nm and about 10 nm.

### Claim 7 (depends on 6)

The epitaxial structure of claim 6, wherein the first barrier layer has a between about 0.5 nm and about 2 nm.

### Claim 8 (depends on 1)

The epitaxial structure of claim 1, further including a back barrier layer between the channel layer and the buffer layer.

### Claim 9 (depends on 1)

The epitaxial structure of claim 1, wherein the first barrier layer and the second barrier layer have a cumulative thickness of at least about 2 nm.

### Claim 10 (depends on 1)

The epitaxial structure of claim 1, wherein the epitaxial structure is a high electron mobility transistor.

### Claim 11 (depends on 10)

The epitaxial structure of claim 10, further including:
a) a source terminal in electrical communication with the second barrier layer;
b) a drain terminal in electrical communication with the second barrier layer; and
c) a gate terminal on the first barrier layer and between the source and drain terminals.

### Claim 12

A method of forming a epitaxial structure, comprising the steps of:
a) forming a substrate;
b) forming a buffer layer on the substrate;
c) forming a channel layer over the buffer layer, the channel layer consisting essentially of InxGa1-xN, where 0≦x≦1;
d) forming a first AlN barrier layer over the channel, the first barrier layer being formed at a first temperature;
e) forming a second AlN barrier layer over the first barrier layer, the second barrier being formed at a temperature lower than that of the first temperature, whereby a two dimensional electron gas forms between the channel and the first barrier layer, and whereby a 2-dimensional electron gas region is formed in the channel layer distal to the buffer layer as a result of forming at least one of the first and second barrier layers; and
f) forming a recess in the second barrier layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the 2-dimensional electron gas region is distal to the buffer layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first barrier layer is of aluminum nitride and is formed at a temperature in a range between about 900° C. and about 1300° C.

### Claim 15 (depends on 14)

The method of claim 14, where the second barrier layer is of aluminum nitride and is formed at a temperature in a range of between about 300° C. and about 900° C.

### Claim 16 (depends on 12)

The method of claim 12, wherein the combined thickness of the first and second barrier layer is greater than about 2 nm.

### Claim 17 (depends on 12)

The method of claim 12, wherein the recess in the second barrier layer is formed by wet etching.

### Claim 18 (depends on 12)

The method of claim 12, wherein the recess in the second barrier layer is formed by dry etching.

### Claim 19 (depends on 18)

The method of claim 18, wherein the dry etching includes reactive ion etching.

### Claim 20 (depends on 18)

The method of claim 18, wherein the dry etching includes inductively-coupled plasma etching

### Claim 21 (depends on 12)

The method of claim 12, further including the step of forming a back barrier layer between the buffer layer and the channel layer.

### Claim 22 (depends on 12)

The method of claim 12, wherein the epitaxial structure formed is a high electron mobility transistor.

### Claim 23 (depends on 22)

The method of claim 22, further including the steps of:
a) forming a source terminal in electrical communication with the second barrier layer;
b) forming a drain terminal in electrical communication with the second barrier layer; and
c) forming a gate terminal on the first barrier layer and between the source and drain terminals.