# US 2014/0151702 A1 · Semiconductor device having chip crack detection structure

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- Number: US 2014/0151702 A1
- Document ID: US20140151702A1
- Status: Published application
- Kind: A1
- Application number: 14/137,857
- Filed: 2013-12-20
- Published: 2014-06-05
- Earliest claimed: 2011-05-18
- Assignees: PS4 Luxco S.a.r.l.
- Inventors: Toru ISHIKAWA
- Web page: https://patentgrep.com/patent/US20140151702A1

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 90/00: Package configurations
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a plurality of signal terminals on each of a plurality of vertically stacked semiconductor chips, each plurality of signal terminals connected to vertically aligned signal terminals of an adjacent semiconductor chip by through silicon vias, a common test terminal on each of the plurality of vertically stacked semiconductor chips connected to a vertically aligned common test terminal of an adjacent semiconductor chip by a through silicon via; a plurality of spiral test terminals on the plurality of vertically stacked semiconductor chips, each spiral test terminal connected to a non-vertically aligned spiral test terminal of an adjacent semiconductor chip by a through silicon via, and a conductive line arranged along a periphery of at least one of the plurality of vertically stacked semiconductor chips, the conductive line connected to a respective common test terminal and a respective spiral test terminal.

## Claims

### Claim 1

A semiconductor device comprising:
a plurality of signal terminals on each of a plurality of vertically stacked semiconductor chips, each plurality of signal terminals connected to vertically aligned signal terminals of an adjacent semiconductor chip by through silicon vias;
a common test terminal on each of the plurality of vertically stacked semiconductor chips connected to a vertically aligned common test terminal of an adjacent semiconductor chip by a through silicon via;
a plurality of spiral test terminals on the plurality of vertically stacked semiconductor chips, each spiral test terminal connected to a non-vertically aligned spiral test terminal of an adjacent semiconductor chip by a through silicon via; and
a conductive line arranged along a periphery of at least one of the plurality of vertically stacked semiconductor chips, the conductive line connected to a respective common test terminal and a respective spiral test terminal.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the conductive line is arranged along the entire of the periphery.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the semiconductor chips are identical chips.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the semiconductor chips are memory chips.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a controller chip connected to the signal terminals of a bottom semiconductor chip of the plurality of vertically stacked semiconductor chips.