# US 2014/0151701 A1 · Embedded chip package, a chip package, and a method for manufacturing an embedded chip package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151701 A1 - Document ID: US20140151701A1 - Status: Published application - Kind: A1 - Application number: 13/705,367 - Filed: 2012-12-05 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Edward Fuergut; Horst Theuss; Walter Diez - Web page: https://patentgrep.com/patent/US20140151701A1 ## CPC - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10D 48/50: Devices controlled by mechanical forces, e.g. pressure - H10P 72/06: {Apparatus for monitoring, sorting, marking, testing or measuring} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 72/00: Interconnections or connectors in packages - H10W 72/0198: {batch processes} - H10W 74/01: Manufacture or treatment - H10W 74/014: {using batch processing} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/874: {On different surfaces} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract An embedded chip package is provided. The embedded chip package includes a plurality of chips; encapsulation material embedding the plurality of chips; at least one electrical redistribution layer electrically connected to the plurality of chips; and a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal. ## Claims ### Claim 1 An embedded chip package comprising: a plurality of chips; encapsulation material embedding the plurality of chips; at least one electrical redistribution layer electrically connected to the plurality of chips; and a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal. ### Claim 2 (depends on 1) The embedded chip package according to claim 1, wherein the encapsulation material at least partially surrounds the plurality of chips. ### Claim 3 (depends on 1) The embedded chip package according to claim 1, wherein the plurality of chips are commonly connected to each other via the encapsulation material. ### Claim 4 (depends on 1) The embedded chip package according to claim 1, wherein at least some of the plurality of chips comprises a sensing portion; and one or more contact pads electrically connected to the sensing portion. ### Claim 5 (depends on 4) The embedded chip package according to claim 4, wherein the encapsulation material covers one or more sides of each of the plurality of chips; and wherein the sensing portions of each of the plurality of chips are substantially free from the encapsulation material. ### Claim 6 (depends on 4) The embedded chip package according to claim 4, wherein the at least one electrical redistribution layer is electrically connected to a respective first contact pad of each of the one or more contact pads. ### Claim 7 (depends on 1) The embedded chip package according to claim 1, wherein the at least one electrical redistribution layer is formed over the encapsulation material in regions between the plurality of chips. ### Claim 8 (depends on 1) The embedded chip package according to claim 1, wherein the common terminal is formed over the encapsulation material in regions between the plurality of chips. ### Claim 9 (depends on 1) The embedded chip package according to claim 1, wherein the common terminal is formed at least partially in the encapsulation material. ### Claim 10 (depends on 6) The embedded chip package according to claim 6, further comprising at least one further electrical redistribution layer; and a further common terminal connected to the at least one further electrical redistribution layer, wherein the further common terminal provides a further interface to at least one of transmit and receive a further common electrical signal between the at least one further electrical redistribution layer and the common terminal; wherein the at least one further electrical redistribution layer is electrically connected to a respective second contact pad of each of the plurality of chips. ### Claim 11 (depends on 1) The embedded chip package according to claim 1, further comprising at least one further chip disposed at least partially in the encapsulation material, wherein the at least one further chip is electrically connected to the plurality of chips. ### Claim 12 (depends on 11) The embedded chip package according to claim 11, wherein the at least one further chip is configured to at least one of transmit and receive the common electrical signal via the common terminal. ### Claim 13 (depends on 10) The embedded chip package according to claim 10, further comprising at least one further chip disposed at least partially in the encapsulation material, wherein the at least one further chip is electrically connected to at least one of the common terminal and the further common terminal. ### Claim 14 (depends on 10) The embedded chip package according to claim 10, wherein the at least one further chip is configured to at least one of transmit and receive the common electrical signal via the common terminal and to at least one of transmit and receive the further common electrical signal via the further common terminal. ### Claim 15 (depends on 14) The embedded chip package according to claim 14, wherein the at least one further chip comprises at least one of a calibrating circuit, a testing circuit and a multiplexing circuit. ### Claim 16 (depends on 4) The embedded chip package according to claim 4, wherein each sensing portion of the plurality of chips comprises at least part of a pressure sensor. ### Claim 17 A method for manufacturing an embedded chip package, the method comprising: embedding a plurality of chips in an encapsulation material; forming at least one electrical redistribution layer over the encapsulation material, the at least one electrical redistribution layer electrically connected to the plurality of chips; forming a common terminal and connecting the common terminal to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal. ### Claim 18 (depends on 17) The method according to claim 17, wherein embedding the plurality of chips in the encapsulation material comprises forming encapsulation material over one or more sides of each of the plurality of chips wherein the sensing portions of each of the plurality of chips are substantially free from the encapsulation material. ### Claim 19 (depends on 17) The method according to claim 17, wherein each chip of the plurality of chips comprises one or more contact pads; and wherein the method further comprises electrically connecting the at least one electrical redistribution layer to a respective first contact pad of each of one or more contact pads. ### Claim 20 (depends on 17) The method according to claim 17, wherein forming the at least one electrical redistribution layer over the encapsulation material comprises forming the at least one electrical redistribution layer in regions between the plurality of chips. ### Claim 21 (depends on 20) The method according to claim 20, further comprising forming the common terminal over the encapsulation material in regions between the plurality of chips. ### Claim 22 (depends on 17) The method according to claim 17, further comprising forming at least one further electrical redistribution layer over the encapsulation material, the at least one further electrical redistribution layer electrically connected to the plurality of chips; and forming a further common terminal and connecting the further common terminal to the at least one further electrical redistribution layer, wherein the further common terminal provides an interface to at least one of transmit and receive a further common electrical signal between the at least one further electrical redistribution layer and the further common terminal. ### Claim 23 (depends on 17) The method according to claim 17, further comprising disposing at least one further chip at least partially in the encapsulation material, wherein the at least one further chip is configured to at least one of transmit and receive the common electrical signal via the common terminal. ### Claim 24 (depends on 22) The method according to claim 22, further comprising disposing at least one further chip at least partially in the encapsulation material, wherein the at least one further chip is configured to at least one of transmit and receive the common electrical signal via the common terminal and to at least one of transmit and receive the further common electrical signal via the further common terminal. ### Claim 25 (depends on 17) The method according to claim 17, further comprising individualizing the plurality of chips from each other by separating through the at least one electrical redistribution layer. ### Claim 26 (depends on 25) The method according to claim 25, further comprising separating the plurality of chips from at least part of the at least one electrical redistribution layer and the common terminal ### Claim 27 A chip package comprising: a chip comprising a sensing portion and one or more contact pads electrically connected to the sensing portion; and an electrical redistribution layer electrically contacting the at least one contact pad, wherein the electrical redistribution layer extends from the at least one contact pad to a sidewall of the chip package, wherein a portion of the electrical redistribution layer is exposed at the sidewall of the chip package. ### Claim 28 (depends on 27) The chip package according to claim 27, further comprising electrically insulating material at least partially surrounding the chip and the electrical redistribution layer, and wherein the portion of the electrical redistribution layer exposed at the sidewall of the chip package electrical redistribution layer is free of electrically insulating material. ### Claim 29 (depends on 27) The chip package according to claim 27, further comprising an electrical interconnect electrically contacting the at least one contact pad and at least partially surrounded by the electrically insulating material, wherein at least part of the electrical interconnect is connected to a solder structure formed over the electrically insulating material.