# US 2014/0151700 A1 · Chip package and a method for manufacturing a chip package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151700 A1 - Document ID: US20140151700A1 - Status: Published application - Kind: A1 - Application number: 13/693,109 - Filed: 2012-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Inventors: Thorsten Meyer; Markus Brunnbauer; Bernd Waidhas - Web page: https://patentgrep.com/patent/US20140151700A1 ## CPC - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 72/5522: {comprising gold [Au]} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A chip package may include an interconnection layer having a first surface configured to face at least one chip, and a second surface opposite the first surface; at least one first pad and at least one second pad formed at at least one of the first surface and the second surface of the interconnection layer; at least one first conductive interconnect formed over the at least one first pad; and at least one second conductive interconnect formed over the at least one second pad, wherein a height of the at least one first conductive interconnect is less than a height of the at least one second conductive interconnect. ## Claims ### Claim 1 A chip package, comprising: an interconnection layer comprising a first surface configured to face at least one chip, and a second surface opposite the first surface; at least one first pad and at least one second pad formed on at least one of the first surface and the second surface of the interconnection layer; at least one first conductive interconnect formed over the at least one first pad; and at least one second conductive interconnect formed over the at least one second pad, wherein a height of the at least one first conductive interconnect is less than a height of the at least one second conductive interconnect. ### Claim 2 (depends on 1) The chip package of claim 1, wherein the at least one first pad comprises a test pad configured to receive one or more test signals. ### Claim 3 (depends on 1) The chip package of claim 1, wherein the at least one second pad comprises at least one pad selected from a group of pads, the group consisting of: an input/output (I/O) pad, a power supply pad, and a ground pad. ### Claim 4 (depends on 1) The chip package of claim 1, wherein the height of the at least one first conductive interconnect is in the range from about 20 μm to about 100 μm. ### Claim 5 (depends on 1) The chip package of claim 1, wherein the height of the at least one second conductive interconnect is in the range from about 200 μm to about 350 μm. ### Claim 6 (depends on 1) The chip package of claim 1, wherein at least one first pad, at least one second pad or a combination of at least one first pad and at least one second pad comprises a metal or a metal alloy. ### Claim 7 (depends on 1) The chip package of claim 1, wherein at least one first conductive interconnect, at least one second conductive interconnect or a combination of at least one first conductive interconnect and at least one second conductive interconnect comprises a metal or a metal alloy. ### Claim 8 (depends on 1) The chip package of claim 1, wherein at least one first conductive interconnect, at least one second conductive interconnect or a combination of at least one first conductive interconnect and at least one second conductive interconnect comprises a solder material. ### Claim 9 (depends on 1) The chip package of claim 1, wherein at least one first conductive interconnect, at least one second conductive interconnect or a combination of at least one first conductive interconnect and at least one second conductive interconnect comprises a solder bump or a lens-shaped solder. ### Claim 10 (depends on 1) The chip package of claim 1, wherein at least one first conductive interconnect, at least one second conductive interconnect or a combination of at least one first conductive interconnect and at least one second conductive interconnect comprises a solder ball. ### Claim 11 (depends on 1) The chip package of claim 1, wherein the interconnection layer comprises a carrier. ### Claim 12 (depends on 1) The chip package of claim 1, wherein the interconnection layer comprises a redistribution layer. ### Claim 13 (depends on 1) The chip package of claim 1, wherein the interconnection layer comprises a semiconductor material. ### Claim 14 (depends on 1) The chip package of claim 1, wherein the interconnection layer comprises a leadframe. ### Claim 15 (depends on 1) The chip package of claim 1, wherein the interconnection layer comprises a carrier, and wherein the at least one first pad and the at least one second pad are formed on the second surface of the interconnection layer. ### Claim 16 (depends on 1) The chip package of claim 1, wherein the interconnection layer comprises a chip-mounting region configured to be coupled to the at least one chip, wherein the chip-mounting region is formed on at least a part of the first surface of the interconnection layer. ### Claim 17 (depends on 1) The chip package of claim 1, further comprising at least one chip disposed over at least a portion of the first surface of the interconnection layer. ### Claim 18 (depends on 17) The chip package of claim 17, wherein an active surface of the at least one chip faces the portion of the first surface of the interconnection layer. ### Claim 19 (depends on 17) The chip package of claim 17, wherein an active surface of the at least one chip faces away from the portion of the first surface of the interconnection layer. ### Claim 20 (depends on 1) The chip package of claim 1, further comprising: a chip-external connection region, wherein the at least one second conductive interconnect couples the interconnection layer to the chip-external connection region. ### Claim 21 (depends on 20) The chip package of claim 20, wherein the chip-external connection region comprises at least one landing pad configured to couple the chip-external connection region to the at least one second conductive interconnect. ### Claim 22 (depends on 20) The chip package of claim 20, wherein the chip-external connection region comprises circuitry configured to exchange at least one of an input/output (I/O) signal, a power supply potential, and a ground potential with the at least one second conductive interconnect. ### Claim 23 A method for manufacturing a chip package, the method comprising: providing an interconnection layer comprising a first surface configured to face at least one chip, and a second surface opposite the first surface; forming at least one first pad and at least one second pad on at least one of the first surface and the second surface of the interconnection layer; forming at least one first conductive interconnect over the at least one first pad; and forming at least one second conductive interconnect over the at least one second pad, wherein a height of the at least one first conductive interconnect is less than a height of the at least one second conductive interconnect. ### Claim 24 (depends on 23) The method of claim 23, wherein forming the at least one first conductive interconnect over the at least one first pad comprises depositing a first conductive material over the at least one first pad. ### Claim 25 (depends on 24) The method of claim 24, wherein the first conductive material comprises a solder paste. ### Claim 26 (depends on 24) The method of claim 24, wherein the first conductive material comprises a metal or metal alloy. ### Claim 27 (depends on 24) The method of claim 24, wherein the first conductive material comprises a solder material. ### Claim 28 (depends on 24) The method of claim 24, wherein depositing the first conductive material over at least the at least one first pad comprises a printing process. ### Claim 29 (depends on 24) The method of claim 24, wherein depositing the first conductive material over at least the at least one first pad comprises a solder jetting process. ### Claim 30 (depends on 24) The method of claim 24, wherein forming the at least one first conductive interconnect over at the at least one first pad further comprises: heating the first conductive material to bond the first conductive material to the at least one first pad. ### Claim 31 (depends on 23) The method of claim 23, wherein forming the at least one second conductive interconnect over the at least one second pad comprises: depositing a first conductive material over the at least one first pad and the at least one second pad; and depositing a second conductive material over the first conductive material over the at least one second pad. ### Claim 32 (depends on 31) The method of claim 31, wherein the second conductive material comprises a metal or metal alloy. ### Claim 33 (depends on 31) The method of claim 31, wherein the second conductive material comprises a solder material. ### Claim 34 (depends on 31) The method of claim 31, wherein the second conductive material comprises a solder ball. ### Claim 35 (depends on 31) The method of claim 31, wherein at least one of depositing the first conductive material over the at least one first pad and the at least one second pad and depositing the second conductive material over the first conductive material over the at least one second pad comprises a printing process. ### Claim 36 (depends on 31) The method of claim 31, wherein at least one of depositing the first conductive material over the at least one first pad and the at least one second pad and depositing the second conductive material over the first conductive material over the at least one second pad comprises a solder jetting process. ### Claim 37 (depends on 31) The method of claim 31, wherein forming the at least one second conductive interconnect over the at least one second pad further comprises: heating the second conductive material and the first conductive material to bond the second conductive material and the first conductive material to the at least one second pad. ### Claim 38 (depends on 23) The method of claim 23, wherein forming the at least one second conductive interconnect over the at least one second pad comprises: depositing a second conductive material over the at least one second pad, wherein the at least one second pad is free from a first conductive material. ### Claim 39 (depends on 38) The method of claim 38, wherein forming the at least one second conductive interconnect over the at least one second pad further comprises: heating the second conductive material to bond the second conductive material to the at least one second pad.