# US 2014/0151699 A1 · Test Structure Placement on a Semiconductor Wafer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151699 A1 - Document ID: US20140151699A1 - Status: Published application - Kind: A1 - Application number: 13/692,414 - Filed: 2012-12-03 - Published: 2014-06-05 - Earliest claimed: 2012-12-03 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, - Inventors: Chuan-Ling Wu; Cheng-Hsien Chuang; Chun-Chang Chen; Wang-Pen Mo; Hung-Chang Hsieh - Web page: https://patentgrep.com/patent/US20140151699A1 ## CPC - H10P 74/27: {Structural arrangements therefor} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures. ## Claims ### Claim 1 A method of fabricating integrated circuit devices, comprising: forming a plurality of spaced integrated circuit dies on a semiconductor wafer; forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data; and forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures. ### Claim 2 (depends on 1) The method according to claim 1, wherein the dedicated test die includes a plurality of test structures formed thereon. ### Claim 3 (depends on 1) The method according to claim 1, wherein the wafer evaluation data includes one or more of critical dimension data, alignment data, overlay error data, and electrical characteristic data. ### Claim 4 (depends on 1) The method according to claim 1, wherein forming the dedicated test die includes forming a plurality of dedicated test dies on the semiconductor wafer. ### Claim 5 (depends on 1) The method according to claim 1, wherein forming the plurality of spaced integrated circuit dies includes forming a square-shaped matrix; and wherein forming the dedicated test die includes placing the dedicated test die at a corner of the square-shaped matrix. ### Claim 6 (depends on 1) The method according to claim 1, wherein each side of the dedicated test die is adjacent a different one of the plurality of integrated circuit dies when viewed in a top view. ### Claim 7 (depends on 1) The method according to claim 1, wherein a ratio of the first width of the test structure to the second width of the scribe line region is at least two. ### Claim 8 (depends on 1) The method according to claim 1, wherein each die of the plurality of spaced integrated circuit dies includes an integrated circuit thereon; and wherein the dedicated test die does not include the integrated circuit. ### Claim 9 (depends on 1) The method according to claim 1, wherein the dedicated test die has smaller dimensions in a top view than each of the spaced integrated circuit dies. ### Claim at position 10 10-17. (canceled) ### Claim 18 A method of fabricating an integrated circuit device, comprising: simulating a semiconductor wafer having an initial number of die regions, a scribe line region interposed between die regions, and a test structure disposed within the scribe line region, the scribe line region having an initial width between die regions in a top view and the test structure having a width in a top view; simulating moving the test structure to within one of the die regions, the scribe line region being free of test structures after the simulating moving; simulating reducing the initial width of the scribe line region to a reduced width such that the reduced width is smaller than the width of the test structure after the simulating reducing; simulating adding additional die regions to the semiconductor wafer; and manufacturing an integrated circuit device on a physical semiconductor wafer based on the simulated semiconductor wafer, the physical semiconductor wafer including: a final number of die regions greater than the initial number of die regions; a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including the test structure formed on the dedicated test die that is disposed within one of the die regions; a plurality of spaced integrated circuit dies formed in respective die regions; the scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having the reduced width. ### Claim 19 (depends on 18) The method according to claim 18, wherein after the simulating reducing the width of the scribe line region, a ratio of the width of the test structure to the width of the scribe line region is at least two. ### Claim 20 (depends on 18) The method according to claim 18, further including, after the manufacturing, performing verification tests on the physical semiconductor wafer using the test structure to generate the wafer evaluation data, the wafer evaluation data including one or more of critical dimension data, alignment data, overlay error data, and electrical characteristic data. ### Claim 21 A method of fabricating integrated circuit devices, comprising: forming a plurality of exposure fields on a wafer, each exposure field in the plurality of exposure fields having a first number of spaced die regions and a scribe line region, the scribe line region interposed between die regions and having a first width being defined by a distance between adjacent die regions when viewed in a top view; forming a second number of integrated circuit dies in respective die regions of each exposure field in the plurality of exposure fields, the second number of integrated circuit dies being less than the first number of die regions; and forming a dedicated test die in one of the die regions in each exposure field in the plurality of exposure fields, the dedicated test die including a test structure having a second width when viewed in a top view and being operable to generate wafer evaluation data, and the second width of the test structure being greater than the first width of the scribe line region; wherein the scribe line region in each exposure field in the plurality of exposure fields is free of test structures. ### Claim 22 (depends on 21) The method of claim 21, wherein the dedicated test die includes a plurality of test structures formed thereon. ### Claim 23 (depends on 21) The method of claim 21, wherein the dedicated test die is one of a plurality of dedicated test dies formed within each exposure field in the plurality of exposure fields. ### Claim 24 (depends on 21) The method of claim 21, wherein the plurality of spaced integrated circuit dies form a square-shaped matrix; and wherein the dedicated test die is disposed at a corner of the square-shaped matrix. ### Claim 25 (depends on 21) The method of claim 21, wherein each side of the dedicated test die is adjacent a different one of the plurality of integrated circuit dies when viewed in a top view. ### Claim 26 (depends on 21) The method of claim 21, wherein a ratio of the second width of the test structure to the first width of the scribe line region is at least two. ### Claim 27 (depends on 21) The method of claim 21, wherein the wafer evaluation data includes one or more of critical dimension data, alignment data, overlay error data, and electrical characteristic data. ### Claim 28 (depends on 21) The method of claim 21, wherein each die of the plurality of spaced integrated circuit dies includes an integrated circuit thereon; wherein the dedicated test die does not include the integrated circuit.