# US 2014/0151698 A1 · Test Structures for Post-Passivation Interconnect

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0151698 A1
- Document ID: US20140151698A1
- Status: Published application
- Kind: A1
- Application number: 13/691,439
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Taiwan Semiconductor Manufactuing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufactuing Company, Ltd.
- Inventors: Hsien-Wei Chen; Jie Chen
- Web page: https://patentgrep.com/patent/US20140151698A1

## CPC

- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 72/01251: {Changing the shapes of bumps}
- H10W 72/0198: {batch processes}
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/147: {the encapsulations being multilayered}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit structure includes a passivation layer, a polymer layer over the passivation layer, and a PPI monitor structure. The PPI monitor structure includes a portion overlying a portion of the polymer layer. The PPI monitor structure is electrically floating.

## Claims

### Claim 1

An integrated circuit structure comprising:
a passivation layer;
a first polymer layer over the passivation layer; and
a Post-Passivation-Interconnect (PPI) monitor structure, wherein the PPI monitor structure comprises a portion overlying a portion of the first polymer layer, and wherein the PPI monitor structure is electrically floating.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein an entirety of the PPI monitor structure is over the first polymer layer.

### Claim 3 (depends on 2)

The integrated circuit structure of claim 2, wherein the PPI monitor structure comprises:
a first portion comprising:
a first PPI pad; and
a first PPI trace connected to the first PPI pad; and
a second portion adjacent to, and is electrical de-coupled from, the first portion, wherein the second portion comprises:
a second PPI pad; and
a second PPI trace connected to the second PPI pad, wherein at least one of the first portion and the second portion is electrically floating.

### Claim 4 (depends on 2)

The integrated circuit structure of claim 2, wherein the PPI monitor structure comprises:
a first PPI pad and a second PPI pad; and
a PPI trace electrically coupling the first PPI pad to the second PPI pad.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, wherein the PPI monitor structure further comprises:
a metal line underlying the first polymer layer;
a first PPI pad, a second PPI pad, and a third PPI pad over the first polymer layer and physically disconnected from each other; and
a first via, a second via, and a third via in the first polymer layer and connecting the first PPI pad, the second PPI pad, and the third PPI pad, respectively, to the metal line.

### Claim 6 (depends on 1)

The integrated circuit structure of claim 1 further comprising a second polymer layer over the first polymer layer, wherein an entirety of the PPI monitor structure is covered by the second polymer layer, with no conductive features penetrating through the second polymer layer and electrically connected to the PPI monitor structure.

### Claim 7 (depends on 1)

The integrated circuit structure of claim 1, wherein the PPI monitor structure is disposed in a scribe line of a wafer, with two chips on opposite sides of the scribe line.

### Claim 8 (depends on 7)

The integrated circuit structure of claim 7, wherein the portion of the first polymer layer is a discrete portion disconnected from all portions of the first polymer layer in the two chips.

### Claim 9

An integrated circuit structure comprising:
a wafer comprising:
a first chip and a second chip;
a scribe line between the first chip and the second chip;
a passivation layer in the wafer;
a first polymer layer in the wafer and over the passivation layer, wherein the first polymer layer comprises:
a first portion in the scribe line; and
second portions in the first chip and the second chip, wherein the first portion is disconnected from all portions of the first polymer layer in the first and the second chips; and
a first Post-Passivation-Interconnect (PPI) monitor structure comprising a portion overlying the first portion of the first polymer layer.

### Claim 10 (depends on 9)

The integrated circuit structure of claim 9, wherein the first PPI monitor structure is electrically floating.

### Claim 11 (depends on 9)

The integrated circuit structure of claim 9, wherein the first portion of the first polymer layer extends beyond edges of the PPI monitor structure by distances smaller than about 15 μm.

### Claim 12 (depends on 9)

The integrated circuit structure of claim 9 further comprising:
a third portion of the first polymer layer in the scribe line, wherein the first and the third portions of the first polymer layer are disconnected from each other; and
a second PPI monitor structure overlapping the third portion of the first polymer layer.

### Claim 13 (depends on 9)

The integrated circuit structure of claim 9 further comprising a second polymer layer over the first polymer layer, wherein the second polymer layer comprises:
a first portion in the scribe line and covering portions of the first PPI monitor structure; and
second portions in the first chip and the second chip, wherein the first portion of the second polymer layer is disconnected from all portions of the second polymer layer in the first and the second chips.

### Claim 14 (depends on 9)

The integrated circuit structure of claim 9 further comprising a second polymer layer over the first polymer layer, wherein the second polymer layer comprises portions in the first chip and the second chip, and wherein the second polymer layer does not comprise portions overlapping the first PPI monitor structure.

### Claim 15

A method comprising:
forming a passivation layer in a wafer;
forming a first polymer layer over the passivation layer;
forming a Post-Passivation-Interconnect (PPI) monitor structure, wherein the PPI monitor structure comprises a portion over the first polymer layer; and
performing a probing to probe the PPI monitor structure, wherein a resistance between probed pads of the PPI monitor structure is measured.

### Claim 16 (depends on 15)

The method of claim 15 further comprising:
forming a second polymer layer over the first polymer layer and the portion of the PPI monitor structure; and
patterning the second polymer layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein after the step of patterning the second polymer layer, an entirety of the PPI monitor structure is covered by a portion of the second polymer layer, and wherein the portion of the second polymer layer is separated from all portions of the second polymer layer in all chips of the wafer.

### Claim 18 (depends on 16)

The method of claim 16, wherein after the step of patterning the second polymer layer, an entirety of the PPI monitor structure is not covered by the second polymer layer.

### Claim 19 (depends on 16)

The method of claim 16 further comprising:
forming Under Bump Metallurgies (UBMs) extending into the second polymer layer and electrically coupled to the PPI monitor structure.

### Claim 20 (depends on 15)

The method of claim 15, wherein the PPI monitor structure is electrically floating.