# US 2014/0151697 A1 · Semiconductor Packages, Systems, and Methods of Formation Thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151697 A1 - Document ID: US20140151697A1 - Status: Published application - Kind: A1 - Application number: 13/691,293 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Udo Ausserlechner; Volker Strutz - Web page: https://patentgrep.com/patent/US20140151697A1 ## CPC - H10W 90/00: Package configurations - G01R 15/207: {Constructional details independent of the type of device used} - H10W 95/00: Packaging processes not covered by the other groups of this subclass - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract In accordance with an embodiment of the present invention, a semiconductor package includes a current rail comprising a first contact area and a second contact area, a first groove and a second groove, and a magnetic field generating portion. Along a current flow direction, the first groove is disposed between the first contact area and the magnetic field generating portion and the second groove is disposed between the magnetic field generating portion and the second contact area. The thickness of the current rail at the first groove is smaller than the thickness of the current rail at the first contact area. ## Claims ### Claim 1 A semiconductor package comprising: a current rail comprising a first contact area and a second contact area, a first groove and a second groove, and a magnetic field generating portion, wherein, along a current flow direction, the first groove is disposed between the first contact area and the magnetic field generating portion and the second groove is disposed between the magnetic field generating portion and the second contact area, wherein a thickness of the current rail at the first groove is smaller than a thickness of the current rail at the first contact area. ### Claim 2 (depends on 1) The package of claim 1, wherein the first and the second contact areas and the first and the second grooves are in a same main surface of the current rail. ### Claim 3 (depends on 1) The package of claim 1, wherein a cross-sectional area of the current rail perpendicular to current flow lines is larger at the first and the second grooves than at the magnetic field generating portion. ### Claim 4 (depends on 1) The package of claim 1, wherein a thickness of the current rail at the first and the second grooves is smaller than a thickness of the current rail at the magnetic field generating portion. ### Claim 5 (depends on 1) The package of claim 1, wherein a thickness of the current rail at the first and the second grooves is smaller than a thickness of the current rail at the first and the second contact areas. ### Claim 6 (depends on 1) The package of claim 1, wherein the first and the second grooves extend substantially perpendicularly to current flow lines due to a current flowing between the first contact area and the second contact area. ### Claim 7 (depends on 1) The package of claim 1, wherein an entire current has to pass across both the first and the second grooves when a current enters at the first contact area and exits at the second contact area. ### Claim 8 (depends on 1) The package of claim 1, further comprising a semiconductor chip mounted parallel to the current rail. ### Claim 9 (depends on 8) The package of claim 8, further comprising a magnetic field sensor disposed within the semiconductor chip. ### Claim 10 (depends on 9) The package of claim 9, wherein the magnetic field sensor is disposed between the first and the second grooves in a plan view. ### Claim 11 (depends on 8) The package of claim 8, further comprising an isolation disposed between the semiconductor chip and the current rail. ### Claim 12 (depends on 8) The package of claim 8, further comprising: a package body securing the current rail, and the semiconductor chip, wherein portions of a back surface of the current rail are exposed at a bottom surface of the package body; and an anti-solder layer covering parts of the exposed portions of the back surface of the current rail, wherein the contact pad regions remain exposed. ### Claim 13 (depends on 12) The package of claim 12, wherein the anti-solder layer comprises a varnish layer. ### Claim 14 (depends on 1) The package of claim 1, wherein the current rail is a flat current rail. ### Claim 15 (depends on 1) The package of claim 1, wherein the magnetic field generating portion comprises a constriction. ### Claim 16 (depends on 1) The package of claim 1, wherein, along a current flow direction within the current rail, a resistance of the first groove is smaller than a resistance of the magnetic field generating portion. ### Claim 17 (depends on 1) The package of claim 1, wherein, a cross-sectional area of the current rail at the first groove along a surface perpendicular to current flow lines is larger than a cross-sectional area of the magnetic field generating portion along a surface perpendicular to current flow lines. ### Claim 18 A semiconductor package comprising: a current rail having contact pad regions and a magnetic field generating portion; a semiconductor chip disposed over the current rail, the semiconductor chip comprising a magnetic field sensor, the magnetic field sensor being proximate the current rail; a package body securing the current rail and the semiconductor chip, wherein portions of a back surface of the current rail are exposed at a bottom surface of the package body; and an anti-solder layer covering first parts of the exposed portions of the back surface of the current rail. ### Claim 19 (depends on 18) The package of claim 18, wherein second parts of the exposed portions of the back surface of the current rail remain exposed. ### Claim 20 (depends on 18) The package of claim 18, further comprising a solder layer disposed on second parts of the exposed portions of the back surface of the current rail. ### Claim 21 (depends on 18) The package of claim 18, further comprising an isolating layer disposed between the current rail and the semiconductor chip. ### Claim 22 (depends on 18) The package of claim 18, wherein the anti-solder layer is configured to prevent a solder material from adhering to the first parts of the exposed portions of the back surface of the current rail. ### Claim 23 (depends on 18) The package of claim 18, wherein the anti-solder layer comprises a varnish, a polymer layer, or a solder resist material. ### Claim 24 (depends on 18) The package of claim 18, wherein the anti-solder layer comprises an insulating layer, wherein the insulating layer comprises a metal oxide layer, a metal nitride layer, or a metal oxynitride. ### Claim 25 (depends on 18) The package of claim 18, wherein a portion of the anti-solder layer separates the magnetic field generating portion from a pad of the contact pad regions. ### Claim 26 (depends on 18) The package of claim 18, wherein the magnetic field generating portion has a first width along a first direction, wherein a pad of the contact pad regions has a second width along the first direction, and wherein the first width is smaller than the second width. ### Claim 27 A system comprising: a circuit board having solder pads; and a semiconductor package coupled to the circuit board through the solder pads, wherein the semiconductor package comprises: a current rail having contact pad regions, a semiconductor chip disposed over the current rail, the semiconductor chip comprising a magnetic field sensor, the magnetic field sensor being proximate the current rail, a package body securing the current rail and the semiconductor chip, wherein portions of a back surface of the current rail are exposed at a bottom surface of the package body facing the circuit board, and an anti-solder layer covering parts of the exposed portions of the back surface of the current rail, wherein the solder pads of the circuit board are disposed under and coupled to the contact pad regions. ### Claim 28 (depends on 27) The system of claim 27, wherein a spacing between the solder pads of the circuit board is less than a spacing between the contact pad regions of the current rail. ### Claim 29 (depends on 27) The system of claim 27, wherein an area of a pad of the solder pads is larger than an area of a pad of the contact pad regions. ### Claim 30 (depends on 27) The system of claim 27, further comprising an isolating layer disposed between the current rail and the semiconductor chip. ### Claim 31 (depends on 27) The system of claim 27, wherein the anti-solder layer is configured to prevent a solder material from adhering to the exposed portions of the back surface of the current rail. ### Claim 32 (depends on 27) The system of claim 27, wherein the anti-solder layer comprises a varnish, a polymer layer, or a solder resist material. ### Claim 33 (depends on 27) The system of claim 27, wherein the anti-solder layer comprises a metal oxide layer, a metal nitride layer, or a metal oxynitride. ### Claim 34 (depends on 27) The system of claim 27, wherein the contact pad regions comprises a first contact area and a second contact area, wherein the current rail comprises a first groove and a second groove, and a magnetic field generating portion, wherein, along a current flow direction, the first groove is disposed between the first contact area and the magnetic field generating portion and the second groove is disposed between the magnetic field generating portion and the second contact area, wherein a thickness of the current rail at the first groove is smaller than a thickness of the current rail at the first contact area. ### Claim 35 A method of forming a semiconductor package, the method comprising: etching a magnetic field generating portion in a lead frame substrate; etching a plurality of grooves in the lead frame substrate, wherein the plurality of grooves are proximate the magnetic field generating portion, wherein the plurality of grooves has a second thickness less than a first thickness of the lead frame substrate, wherein, in a plan view, the magnetic field generating portion is disposed between a first groove of the plurality of grooves and a second groove of the plurality of grooves; and attaching a semiconductor chip over the lead frame substrate, the semiconductor chip being proximate the magnetic field generating portion. ### Claim 36 (depends on 35) The method of claim 35, further comprising: forming a package body securing the lead frame substrate and the semiconductor chip, wherein portions of a back surface of the lead frame substrate are exposed at a bottom surface of the package body; and forming an anti-solder layer under parts of the exposed portions of the back surface of the lead frame substrate. ### Claim 37 (depends on 36) The method of claim 36, further comprising forming a solder layer under the lead frame substrate. ### Claim 38 (depends on 36) The method of claim 36, wherein the magnetic field generating portion has a third thickness less than the first thickness. ### Claim 39 A method of forming a semiconductor package, the method comprising: providing a lead frame substrate having a magnetic field generating portion; attaching a semiconductor chip over the magnetic field generating portion, the semiconductor chip comprising a magnetic field sensor disposed proximate the magnetic field generating portion; forming a package body securing the lead frame substrate and the semiconductor chip, wherein portions of a back surface of the lead frame substrate are exposed at a bottom surface of the package body; and forming an anti-solder layer under parts of the exposed portions of the back surface of the lead frame substrate. ### Claim 40 (depends on 39) The method of claim 39, wherein forming the anti-solder layer comprises applying a solder resist material. ### Claim 41 (depends on 39) The method of claim 39, wherein forming the anti-solder layer comprises using a printing process.