# US 2014/0151692 A1 · Semiconductor device and method for manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151692 A1 - Document ID: US20140151692A1 - Status: Published application - Kind: A1 - Application number: 14/172,072 - Filed: 2014-02-04 - Published: 2014-06-05 - Earliest claimed: 2010-03-08 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Hiromichi GODO; Ryota IMAHAYASHI; Kiyoshi KATO - Web page: https://patentgrep.com/patent/US20140151692A1 ## CPC - H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes} - H10D 30/6725: {having supplementary regions or layers for improving the flatness of the device} - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/60: wherein the TFTs are in active matrices - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Disclosed is a semiconductor device including: an insulating layer; a source electrode and a drain electrode embedded in the insulating layer; an oxide semiconductor layer in contact and over the insulating layer, the source electrode, and the drain electrode; a gate insulating layer over and covering the oxide semiconductor layer; and a gate electrode over the gate insulating layer, where the upper surfaces of the insulating layer, the source electrode, and the drain electrode exist coplanarly. The upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less, and the difference in height between the upper surface of the insulating layer and the upper surface of the source electrode or the drain electrode is less than 5 nm. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization. ## Claims ### Claim 1 (canceled) ### Claim 2 A semiconductor device comprising: a transistor comprising: an intrinsic oxide semiconductor layer including a channel formation region; a gate insulating layer over the intrinsic oxide semiconductor layer; a gate electrode over the gate insulating layer, and a source electrode and a drain electrode each electrically connected to the intrinsic oxide semiconductor layer, wherein a first edge side of the gate electrode overlaps with an edge side of the source electrode, wherein a second edge side of the gate electrode, which is opposed to the first edge side of the gate electrode, overlaps with an edge side of the drain electrode, and wherein the edge side of the source electrode is opposed to the edge side of the drain electrode. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the first edge side is parallel to the edge side of the source electrode, and wherein the second edge side is parallel to the edge side of the drain electrode. ### Claim 4 (depends on 2) The semiconductor device according to claims 2, wherein a length of the channel formation region is defined by a distance between the edge side of the source electrode and the edge side of the drain electrode. ### Claim 5 (depends on 2) The semiconductor device according to claim 2, wherein a thickness of the intrinsic oxide semiconductor layer is equal to or larger than 1 nm and equal to or smaller than 50 nm. ### Claim 6 (depends on 2) The semiconductor device according to claim 2, wherein a carrier density of the intrinsic oxide semiconductor layer is less than 1×1014/cm3. ### Claim 7 (depends on 2) The semiconductor device according to claim 2, wherein a hydrogen concentration of the intrinsic oxide semiconductor layer, which is determined by secondary ion mass spectrometry, is equal to or less than 5×1019 atoms/cm3. ### Claim 8 (depends on 2) The semiconductor device according to claim 2, wherein an off-state current per a channel width of the transistor is equal to or less than 100 zA/μm. ### Claim 9 (depends on 2) The semiconductor device according to claim 2, wherein the intrinsic oxide semiconductor layer comprises at least one of In, Ga, Sn, and Zn. ### Claim 10 (depends on 2) An electronic device comprising the semiconductor device according to claim 2. ### Claim 11 A semiconductor device comprising: a first transistor comprising: a semiconductor substrate including a pair of impurity regions and a first channel formation region which is sandwiched between the pair of impurity regions; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer; an insulating layer over the pair of impurity regions; and a second transistor over the insulating layer, the second transistor comprising: an intrinsic oxide semiconductor layer including a second channel formation region; a second gate insulating layer over the intrinsic oxide semiconductor layer; a second gate electrode over the second gate insulating layer, and a source electrode and a drain electrode each electrically connected to the intrinsic oxide semiconductor layer, wherein a first edge side of the second gate electrode overlaps with an edge side of the source electrode, wherein a second edge side of the second gate electrode, which is opposed to the first edge side of the second gate electrode, overlaps with an edge side of the drain electrode, and wherein the edge side of the source electrode is opposed to the edge side of the drain electrode. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the first edge side is parallel to the edge side of the source electrode, and wherein the second edge side is parallel to the edge side of the drain electrode. ### Claim 13 (depends on 11) The semiconductor device according to claim 11, wherein a length of the second channel formation region is defined by a distance between the edge side of the source electrode and the edge side of the drain electrode. ### Claim 14 (depends on 11) The semiconductor device according to claim 11, wherein a thickness of the intrinsic oxide semiconductor layer is equal to or larger than 1 nm and equal to or smaller than 50 nm. ### Claim 15 (depends on 11) The semiconductor device according to claim 11, wherein a carrier density of the intrinsic oxide semiconductor layer is less than 1×1014/cm3. ### Claim 16 (depends on 11) The semiconductor device according to claim 11, wherein a hydrogen concentration of the intrinsic oxide semiconductor layer, which is determined by secondary ion mass spectrometry, is equal to or less than 5×1019 atoms/cm3. ### Claim 17 (depends on 11) The semiconductor device according to claim 11, wherein an off-state current per a channel width of the second transistor is equal to or less than 100 zA/μm. ### Claim 18 (depends on 11) The semiconductor device according to claim 11, wherein the intrinsic oxide semiconductor layer comprises at least one of In, Ga, Sn, and Zn. ### Claim 19 (depends on 11) An electronic device comprising the semiconductor device according to claim 11. ### Claim 20 A semiconductor device comprising: an oxide semiconductor layer over an insulating surface, the oxide semiconductor layer including a channel formation region; a source electrode and a drain electrode each in contact with the oxide semiconductor layer; a gate insulating layer over the oxide semiconductor layer; and a gate electrode over the channel formation region with the gate insulating layer therebetween, wherein end portions of the gate electrode overlap with an end portion of the source electrode and an end portion of the drain electrode, wherein at least a portion of the insulating surface has a root-mean-square roughness of 1 nm or less, and wherein the portion and the channel formation region overlap with each other. ### Claim 21 (depends on 20) The semiconductor device according to claim 20, wherein the source electrode and the drain electrode are located under the oxide semiconductor layer. ### Claim 22 A method for manufacturing a semiconductor device, the method comprising: forming an oxide semiconductor layer, a source electrode, and a drain electrode over a substrate; forming a gate insulating layer over the oxide semiconductor layer; forming a gate electrode over the gate insulating layer so that a first edge side of the gate electrode overlaps with an edge side of the source electrode and a second edge side of the gate electrode, which is opposed to the first edge side of the gate electrode, overlaps with an edge side of the drain electrode; and performing heat treatment on the oxide semiconductor layer so as to become intrinsic, wherein the edge side of the source electrode is opposed to the edge side of the drain electrode. ### Claim 23 (depends on 22) The method according to claims 22, wherein the oxide semiconductor layer comprises at least one of In, Ga, Sn, and Zn.