# US 2014/0151687 A1 · Semiconductor device and manufacturing method thereof

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- Number: US 2014/0151687 A1
- Document ID: US20140151687A1
- Status: Published application
- Kind: A1
- Application number: 14/091,568
- Filed: 2013-11-27
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei YAMAZAKI
- Web page: https://patentgrep.com/patent/US20140151687A1

## CPC

- H10D 86/0229: {characterised by control of the annealing or irradiation parameters}
- G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)}
- G02F 1/1341: Filling or closing of cells
- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- G02F 1/136213: {Storage capacitors associated with the pixel electrode}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- H10D 62/8271: {comprising only oxide semiconductor materials heterojunctions, e.g. IGZO/IZO}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D 62/875: {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874)}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In a semiconductor device, a region where a channel is formed is protected. In a semiconductor device, a region protecting a region where a channel is formed is provided in a semiconductor layer. In a semiconductor device, a layer protecting a region where a channel is formed is provided. In a semiconductor device, a region and/or a layer protecting a region where a channel is formed have/has a low density of defect states. In a semiconductor device, a region where a channel is formed has a low density of defect states.

## Claims

### Claim 1

A semiconductor device comprising:
an oxide semiconductor layer;
a gate insulating film in contact with the oxide semiconductor layer; and
a gate electrode overlapping with the oxide semiconductor layer with the gate insulating film provided between the gate electrode and the oxide semiconductor layer,
wherein a first region is included in a range from a top surface to a 5 nm depth of the oxide semiconductor layer and has a larger energy gap than a second region in a depth of greater than or equal to 5 nm from the top surface of the oxide semiconductor layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
an electrode over the oxide semiconductor layer with a second oxide semiconductor layer provided between the oxide semiconductor layer and the electrode,
wherein the second oxide semiconductor layer comprises a third region having a larger energy gap than the second region.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein the oxide semiconductor layer is in contact with an insulating film containing silicon on a side facing the gate insulating film and comprises a channel region which is apart from the insulating film.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the gate insulating film is provided over the gate electrode and the oxide semiconductor layer is provided over the gate insulating film.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1,
wherein the oxide semiconductor layer contains indium and at least one of aluminum, gallium, yttrium, zirconium, and tin.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1,
wherein the oxide semiconductor layer is one of a c-axis aligned crystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer, a microcrystalline oxide semiconductor layer, and an amorphous oxide semiconductor layer.

### Claim 7

A semiconductor device comprising:
an oxide semiconductor layer containing indium and an element M, wherein M represents aluminum, gallium, yttrium, zirconium, or tin;
a gate insulating film in contact with the oxide semiconductor layer; and
a gate electrode overlapping with the oxide semiconductor layer with the gate insulating film provided between the gate electrode and the oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a region where a proportion of the indium is lower than a proportion of the element M in a range from a top surface to a 5 nm depth of the oxide semiconductor layer.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, further comprising:
an electrode over the oxide semiconductor layer with a second oxide semiconductor layer provided between the oxide semiconductor layer and the electrode,
wherein the second oxide semiconductor layer comprises a third region having a larger energy gap than a second region in a depth of greater than or equal to 5 nm from the top surface of the oxide semiconductor layer.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7,
wherein the oxide semiconductor layer is in contact with an insulating film containing silicon on a side facing the gate insulating film and comprises a region in which a channel is formed in a region apart from the insulating film.

### Claim 10 (depends on 7)

The semiconductor device according to claim 7,
wherein the gate insulating film is provided over the gate electrode and the oxide semiconductor layer is provided over the gate insulating film.

### Claim 11 (depends on 7)

The semiconductor device according to claim 7,
wherein the oxide semiconductor layer is one of a c-axis aligned crystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer, a microcrystalline oxide semiconductor layer, an amorphous oxide semiconductor layer

### Claim 12

A method for manufacturing a semiconductor device comprising the steps of:
forming a gate electrode;
forming a gate insulating film over the gate electrode;
forming a first oxide semiconductor layer over the gate insulating film and forming a second oxide semiconductor layer over the first oxide semiconductor layer,
forming a conductive film over the second oxide semiconductor layer; and
partly etching the conductive film to expose a part of the second oxide semiconductor layer,
wherein the part of the second oxide semiconductor layer is etched so that a thickness of the part of the second oxide semiconductor layer is greater than or equal to 0 nm and less than 5 nm.

### Claim 13 (depends on 12)

The method for manufacturing a semiconductor device according to claim 12,
wherein the second oxide semiconductor layer comprises a region having a larger energy gap than the energy gap of the first oxide semiconductor layer.

### Claim 14 (depends on 12)

The method for manufacturing a semiconductor device according to claim 12,
wherein the second oxide semiconductor layer and the first oxide semiconductor layer comprise indium and an element M selected from aluminum, gallium, yttrium, zirconium, and tin, and
wherein the second oxide semiconductor layer comprises a region where a proportion of the element M is higher than a proportion of the element M in the first oxide semiconductor layer.

### Claim 15 (depends on 12)

The method for manufacturing a semiconductor device according to claim 12,
wherein the second oxide semiconductor layer is formed by a sputtering method at a substrate temperature of higher than or equal to 100° C. and lower than 500° C.

### Claim 16 (depends on 12)

The method for manufacturing a semiconductor device according to claim 12,
wherein a mixed region of the first oxide semiconductor layer and the second oxide semiconductor layer is formed between the first oxide semiconductor layer and the second oxide semiconductor layer.