# US 2014/0151682 A1 · Circuit board, display device, and process for production of circuit board > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151682 A1 - Document ID: US20140151682A1 - Status: Published application - Kind: A1 - Application number: 13/810,113 - Filed: 2011-04-13 - Published: 2014-06-05 - Earliest claimed: 2010-07-15 - Assignees: Sharp Kabushiki Kaisha - Inventors: Yuichi Saito; Yohsuke Kanzaki; Yudai Takanishi; Tetsuya Okamoto; Yoshiki Nakatani; Yoshimasa Chikama - Web page: https://patentgrep.com/patent/US20140151682A1 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 62/80: characterised by the materials - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/0231: {using masks, e.g. half-tone masks} - H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)} - H10P 50/20: Dry etching; Plasma etching; Reactive-ion etching - H10P 50/667: {by liquid etching only} - H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices - H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass - H10P 95/70: Chemical treatments - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 20/4424: {Copper alloys} - G02F 1/133302: {Rigid substrates, e.g. inorganic substrates} - G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)} - G02F 1/134336: {Matrix} - G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making} - G02F 1/136231: {for reducing the number of lithographic steps} - G02F 1/136236: {using a grey or half tone lithographic process} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/136295: {Materials; Compositions; Manufacture processes} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - H10D 64/011: {of electrodes ohmically coupled to a semiconductor} - H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering - H10P 14/3426: {Oxides} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract The present invention provides a circuit board having excellent productivity, particularly a circuit board having excellent productivity with respect to a semiconductor layer and source layer forming step, a display device, and a process for producing a circuit board. The circuit board of the present invention is a circuit board including an oxide semiconductor layer and an electrode connected to the oxide semiconductor layer, wherein the electrode is formed by essentially laminating a layer made of a metal other than copper and a layer containing copper. ## Claims ### Claim 1 A circuit board comprising: an oxide semiconductor layer; and an electrode which is connected to the oxide semiconductor layer, wherein the electrode is formed by essentially laminating a layer made of a metal other than copper and a layer containing copper. ### Claim 2 (depends on 1) The circuit board according to claim 1, wherein the layer made of a metal other than copper contains at least one selected from a group consisting of titanium and molybdenum. ### Claim 3 (depends on 1) The circuit board according to claim 1, wherein the oxide semiconductor layer is formed of indium gallium zinc composite oxide. ### Claim 4 (depends on 1) The circuit board according to claim 1, wherein the electrode includes a source electrode and a drain electrode, and the source electrode and the drain electrode include portions connected to the oxide semiconductor layer, respectively, and the portion of the source electrode which is connected to the semiconductor layer and the portion of the drain electrode which is connected to the semiconductor layer face each other with a gap interposed therebetween. ### Claim 5 (depends on 4) The circuit board according to claim 4, wherein the portion of the source electrode which is connected to the semiconductor layer and the portion of the drain electrode connected to the semiconductor layer are located further inside than the semiconductor layer when a main surface of the board is seen in plan view. ### Claim 6 (depends on 1) A display device comprising the circuit board according to claim 1. ### Claim 7 A process for producing a circuit board including an oxide semiconductor layer and an electrode connected to the oxide semiconductor layer, the process comprising: a semiconductor layer forming step of forming an oxide semiconductor layer; an electric conductor layer forming step of forming an electric conductor layer by essentially laminating a layer made of a metal other than copper and a layer containing copper; and a processing step of processing the electric conductor layer by using wet etching, wherein the processing step includes forming the electrode. ### Claim 8 (depends on 7) The process for producing a circuit board according to claim 7, wherein the processing step includes a first etching step of etching the electric conductor layer and the oxide semiconductor layer and a second etching step of etching the electric conductor layer by using wet etching, and the second etching step separates the electric conductor layer into a source electrode and a drain electrode, and causes a portion of the source electrode which is connected to the semiconductor layer and a portion of the drain electrode which is connected to the semiconductor layer to face each other with a gap interposed therebetween. ### Claim 9 (depends on 8) The process for producing a circuit board according to claim 8, wherein in the first etching step and/or the second etching step, the layer containing copper is etched by using an etchant containing hydrogen peroxide and an acid. ### Claim 10 (depends on 8) The process for producing a circuit board according to claim 8, wherein the layer made of a metal other than copper is a layer made of a metal containing molybdenum, and in the first etching step and/or the second etching step, the layer made of a metal containing molybdenum is etched by using an etchant containing hydrogen peroxide and an acid. ### Claim 11 (depends on 8) The process for producing a circuit board according to claim 8, wherein in the first etching step and/or the second etching step, the layer containing copper is etched by using an alkaline etchant. ### Claim 12 (depends on 8) The process for producing a circuit board according to claim 8, wherein the layer made of a metal other than copper is a layer made of a metal containing titanium, and in the first etching step and/or the second etching step, the layer made of a metal containing titanium is etched by using an alkaline etchant. ### Claim at position 13 13-14. (canceled) ### Claim 15 (depends on 8) The process for producing a circuit board according to claim 8, wherein in the first etching step, the oxide semiconductor layer is etched by using an etchant containing oxalic acid. ### Claim 16 (depends on 7) The process for producing a circuit board according to claim 7, wherein the processing step includes a gap portion etching step of etching the electric conductor layer by using wet etching, and the gap portion etching step separates the electric conductor layer into a source electrode and a drain electrode, and causes a portion of the source electrode which is connected to the semiconductor layer and a portion of the drain electrode which is connected to the semiconductor layer to face each other with a gap interposed therebetween. ### Claim 17 (depends on 16) The process for producing a circuit board according to claim 16, wherein in the gap portion etching step, the layer containing copper is etched by using an etchant containing hydrogen peroxide and an acid. ### Claim 18 (depends on 16) The process for producing a circuit board according to claim 16, wherein the layer made of a metal other than copper is a layer made of a molybdenum-based metal, and in the gap portion etching step, the layer made of a molybdenum-based metal is etched by using an etchant containing hydrogen peroxide and an acid. ### Claim 19 (depends on 16) The process for producing a circuit board according to claim 16, wherein in the gap portion etching step, the layer containing copper is etched by using an alkaline etchant. ### Claim 20 (depends on 16) The process for producing a circuit board according to claim 16, wherein the layer made of a metal other than copper is a layer made of a titanium-based metal, and in the gap portion etching step, the layer made of a titanium-based metal is etched by using an alkaline etchant. ### Claim at position 20 21-22. (canceled) ### Claim 23 (depends on 16) The process for producing a circuit board according to claim 16, wherein in the semiconductor layer forming step, the oxide semiconductor layer is etched by using an etchant containing oxalic acid. ### Claim 24 (depends on 7) The process for producing a circuit board according to claim 7, wherein the oxide semiconductor layer is formed of indium gallium zinc composite oxide.