# US 2014/0151679 A1 · Method of forming a top gate transistor

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- Number: US 2014/0151679 A1
- Document ID: US20140151679A1
- Status: Published application
- Kind: A1
- Application number: 14/234,132
- Filed: 2012-07-13
- Published: 2014-06-05
- Earliest claimed: 2011-07-21
- Assignees: Cambridge Display Technology Limited
- Inventors: Arne Fleissner
- Web page: https://patentgrep.com/patent/US20140151679A1

## CPC

- H10K 10/46: Field-effect transistors, e.g. organic thin-film transistors [OTFT] (H10K10/43 takes precedence)
- H10K 10/464: {Lateral top-gate IGFETs comprising only a single gate}
- H10K 10/471: {the gate dielectric comprising only organic materials}
- H10K 10/481: {characterised by the gate conductors}
- H10K 71/621: {Providing a shape to conductive layers, e.g. patterning or selective deposition}
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A method of forming a top-gate transistor over a substrate comprises: forming a source and a drain electrode; forming an organic stack over the source and drain electrodes comprising an organic semiconductor layer and an organic dielectric layer over the organic semiconductor layer; forming a gate bi-layer electrode comprising a first gate layer of a first material and a second gate layer of a different second material; selectively depositing regions of a mask material over the gate bi-layer electrode; performing a first plasma etch step to remove portions of the first gate layer using the mask material as a mask; and performing a second plasma etch step to remove portions of the second gate layer and organic stack using the first gate layer as a mask, thereby patterning the gate bi-layer electrode and the organic stack.

## Claims

### Claim 1

A method of forming a top-gate transistor over a substrate, the method comprising:
forming a source and a drain electrode over the substrate;
forming an organic stack over the substrate and the source and drain electrodes, the organic stack comprising an organic semiconductor layer over the substrate and the source and drain electrodes and an organic dielectric layer over the organic semiconductor layer;
forming a gate bi-layer electrode comprising a first gate layer of a first material and a second gate layer of a different second material, the first gate layer being formed over the second gate layer, and the second gate layer being formed over the organic stack;
selectively depositing regions of a mask material over the gate bi-layer electrode;
performing a first plasma etch step to remove portions of the first gate layer using the mask material as a mask; and
performing a second plasma etch step to remove portions of the second gate layer and organic stack using the first gate layer as a mask, thereby patterning the gate bi-layer electrode and the organic stack.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second plasma etch step also further comprises removing the mask material.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second gate layer is substantially thicker than the first gate layer.

### Claim 4

(canceled)

### Claim 5

(canceled)

### Claim 6 (depends on 1)

The method of claim 1, wherein the material of the first gate layer is selected from the group consisting of aluminum, chromium, nickel and alloys thereof.

### Claim 7 (depends on 1)

The method of claim 1, wherein the material of the first gate layer is one of Al2O3, MgO and Sc2O3.

### Claim 8

(canceled)

### Claim 9 (depends on 1)

The method of claim 1, wherein the material of the second gate layer is one of titanium, tungsten, molybdenum, tantalum, niobium and alloys thereof.

### Claim 10

(canceled)

### Claim 11 (depends on 1)

The method of claim 1, comprising performing the first plasma etch step by means of an argon plasma sputter etch.

### Claim 12 (depends on 1)

The method of claim 1, comprising performing the first plasma etch step by means of a chlorine plasma etch.

### Claim 13 (depends on 1)

The method of claim 1, comprising performing the second plasma etch step by means of an oxygen-fluorine plasma etch.

### Claim 14 (depends on 1)

The method of claim 1, wherein the mask material comprises an organic mask material.

### Claim 15 (depends on 1)

The method of claim 1, comprising selectively depositing regions of the mask material by ink-jet printing.

### Claim 16

A top-gate transistor formed over a substrate, the top-gate transistor comprising:
a source and a drain electrode formed over the substrate;
an organic stack formed over the substrate and the source and drain electrodes, the organic stack comprising an organic semiconductor layer over the substrate and the source and drain electrodes and an organic dielectric layer over the organic semiconductor layer; and
a gate bi-layer electrode formed over the organic stack comprising a first gate layer of a first material and a second gate layer of a different second material, the first gate layer being formed over the second gate layer, and the second gate layer being formed over the organic stack.

### Claim 17 (depends on 16)

The top-gate transistor of claim 16, wherein the second gate layer is substantially thicker than the first gate layer.

### Claim 18 (depends on 16)

The top-gate transistor of claim 16, wherein the first gate layer has a thickness of between 2 nm and 200 nm.

### Claim 19 (depends on 16)

The top-gate transistor of claim 16, wherein the second gate layer has a thickness of between 20 nm and 500 nm.

### Claim 20

(canceled)

### Claim 21

(canceled)

### Claim 22 (depends on 16)

The top-gate transistor of claim 16, wherein the material of the first gate layer is aluminum aluminium.

### Claim 23

(canceled)

### Claim 24 (depends on 16)

The top-gate transistor of claim 16, wherein the material of the second gate layer is titanium.

### Claim at position 25

25-29. (canceled)