# US 2014/0151675 A1 · Semiconductor device and manufacturing method thereof

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- Number: US 2014/0151675 A1
- Document ID: US20140151675A1
- Status: Published application
- Kind: A1
- Application number: 14/174,494
- Filed: 2014-02-06
- Published: 2014-06-05
- Earliest claimed: 2005-05-31
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Toshihiko SAITO
- Web page: https://patentgrep.com/patent/US20140151675A1

## CPC

- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- H10B 10/00: Static random access memory [SRAM] devices
- H10D 1/68: Capacitors having no potential barriers
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10K 19/80: Interconnections, e.g. terminals
- H10D 86/40: characterised by multiple TFTs
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

An object of the invention is to reduce an area occupied by a capacitor in a circuit in a semiconductor device, and to downsize a semiconductor device on which the capacitor and an organic memory are mounted. The organic memory and the capacitor, included in a peripheral circuit, in which the same material as the layer containing the organic compound used for the organic memory is used as a dielectric, are used. The peripheral circuit here means a circuit having at least a capacitor such as a resonance circuit, a power supply circuit, a boosting circuit, a DA converter, or a protective circuit. Further, a capacitor in which a semiconductor is used as a dielectric may be provided over the same substrate as well as the capacitor in which the same material as the layer containing the organic compound is used as a dielectric. In this case, it is desirable that the capacitor in which the same material as the layer containing the organic compound is used as a dielectric and the capacitor in which the semiconductor is used as a dielectric are connected to each other in parallel.

## Claims

### Claim 1

(canceled)

### Claim 2

A semiconductor device comprising:
a semiconductor layer over an insulating surface, the semiconductor layer comprising an oxide semiconductor;
a gate insulating layer over the semiconductor layer; and
a gate wiring over the semiconductor layer with the insulating layer therebetween.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein at least one part of the gate insulating layer includes silicon oxide or silicon nitride.

### Claim 4

A semiconductor device comprising:
a semiconductor layer over an insulating surface, the semiconductor layer comprising an oxide semiconductor;
a gate insulating layer over the semiconductor layer;
a gate wiring over the semiconductor layer with the insulating layer therebetween;
an interlayer insulating layer over the gate wiring;
a wiring over the interlayer insulating layer, the wiring electrically connected to the semiconductor layer.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein at least one part of the gate insulating layer includes silicon oxide or silicon nitride.

### Claim 6 (depends on 4)

The semiconductor device according to claim 4, wherein the interlayer insulating layer is formed using silicon oxide, polyimide or acrylic resin.

### Claim 7 (depends on 4)

The semiconductor device according to claim 4, further comprising a first insulating layer between the gate wiring and the interlayer insulating layer.

### Claim 8 (depends on 4)

The semiconductor device according to claim 4, further comprising a second insulating layer between the interlayer insulating layer and the wiring.

### Claim 9 (depends on 4)

The semiconductor device according to claim 4, wherein the wiring includes stacked layers.

### Claim 10 (depends on 4)

The semiconductor device according to claim 4,
wherein the interlayer insulating layer has a contact hole, and
wherein the wiring is in contact with the semiconductor layer through a contact hole.