# US 2014/0151644 A1 · Heterojunction tunneling field effect transistors, and methods for fabricating the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0151644 A1
- Document ID: US20140151644A1
- Status: Published application
- Kind: A1
- Application number: 14/088,808
- Filed: 2013-11-25
- Published: 2014-06-05
- Earliest claimed: 2006-02-01
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Xiangdong Chen; Haining S. Yang
- Web page: https://patentgrep.com/patent/US20140151644A1

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 12/021: {of gated diodes, e.g. field-controlled diodes [FCD]}
- H10D 12/211: {Gated diodes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

## Claims

### Claim 1

A tunneling field effect transistor (TFET) comprising:
a first device region including a first drain region of n-type conductivity silicon, a first source region of p-type conductivity silicon germanium, a first channel region of an n-type conductivity between the first source region and the first drain region, and a first gate stack located over the first channel region; and
a second device region including a second drain region of p-type conductivity silicon, a second source region of n-type conductivity Si:C, a second channel region of a p-type conductivity between the second source region and the second drain region, and a second gate stack located over the second channel region.

### Claim 2 (depends on 1)

The TFET of claim 1, wherein the second source region has a carbon concentration ranging from about 1 atomic % to about 5 atomic % at a junction immediately adjacent to the second channel region.

### Claim 3 (depends on 1)

The TFET of claim 1, wherein the second source region, second drain, and the second channel regions are located in an n-well of a semiconductor substrate.

### Claim 4 (depends on 3)

The TFET of claim 3, wherein the second source region of the n-type conductivity Si:C has a smaller band gap than silicon.

### Claim 5 (depends on 3)

The TFET of claim 3, wherein at least one of the first channel region and the second channel region has a channel length ranging from about 0.2 μm to about 10 μm.

### Claim 6 (depends on 3)

The TFET of claim 3, wherein at least one of the first channel region and the second channel region has a channel width ranging from about 0.02 μm to about 10 μm.

### Claim 7 (depends on 3)

The TFET of claim 3, wherein the first source region has a germanium concentration ranging from about 10 atomic % to about 30 atomic % at a junction immediately adjacent to the first channel region.

### Claim 8 (depends on 3)

The TFET of claim 3, wherein the first source region, the first drain region, and the first channel region are located in a p-well of a semiconductor substrate.

### Claim 9 (depends on 3)

The TFET of claim 3, wherein at least one of the first gate structure and the second gate structure including at least one gate dielectric and at least one gate conductor.

### Claim 10

A semiconductor device comprising:
a semiconductor substrate,
a tunneling field effect transistor (TFET) comprising spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region, wherein the source, drain, and channel regions of the TFET are located in the semiconductor substrate, wherein the drain region of the TFET comprises silicon of an n-type conductivity, wherein the source region of the TFET comprises silicon germanium of a p-type conductivity, and wherein the gate stack of the TFET comprises at least a gate dielectric and a gate conductor; and
a metal-oxide-semiconductor field effect transistor (MOSFET) adjacent to the TFET, wherein the MOSFET comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region, and wherein the source, drain, and channel regions of the MOSFET are located in the semiconductor substrate.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the source region of the TFET has a germanium concentration ranging from about 10 atomic % to about 30 atomic %.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the silicon germanium of the p-type conductivity has a larger band gap than silicon.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the channel region of the TFET has a channel length ranging from about 0.2 μm to about 10 μm, and a channel width ranging from about 0.02 μm to about 10 μm.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the second source region, second drain, and the second channel regions are located in an n-well of a semiconductor substrate.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein the TFET includes a gate structure including a gate conductor and a gate dielectric.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the gate dielectric is selected from the group consisting of hafnium oxide (HfO2), hafnium silicate (HfSiOx), hafnium silicon oxynitride (HfSiON), a mixture of hafnium oxide and zirconium oxide (ZrO2), and combinations thereof.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the gate conductor comprises a metal, metal alloy, metal nitride, metal silicide, a semiconductor material comprising Si or SiGe alloy, or a combination thereof.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the MOSFET includes a gate structure including a gate conductor and a gate dielectric.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the gate dielectric is selected from the group consisting of hafnium oxide (HfO2), hafnium silicate (HfSiOx), hafnium silicon oxynitride (HfSiON), a mixture of hafnium oxide and zirconium oxide (ZrO2), and combinations thereof.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein the gate conductor comprises a metal, metal alloy, metal nitride, metal silicide, a semiconductor material comprising Si or SiGe alloy, or a combination thereof.