# US 2014/0151643 A1 · Self-aligned double-gate graphene transistor

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- Number: US 2014/0151643 A1
- Document ID: US20140151643A1
- Status: Published application
- Kind: A1
- Application number: 13/971,071
- Filed: 2013-08-20
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Damon B. Farmer; Aaron D. Franklin; Joshua T. Smith
- Web page: https://patentgrep.com/patent/US20140151643A1

## CPC

- H10D 62/882: {Graphene}
- H10D 30/01: Manufacture or treatment
- H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 48/01: Manufacture or treatment
- H10D 62/8303: {Diamond}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P 14/3406: {Carbon, e.g. diamond-like carbon}
- Y10S 977/734: Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.

## Claims

### Claim 1

A semiconducting device, comprising:
a graphene sheet formed on a substrate;
a first contact coupled to the graphene sheet and a second contact coupled to the graphene sheet and separated from the first contact by a gap;
at least one slot formed in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and
a recess formed in the substrate beneath the graphene sheet via etchant passing through the graphene sheet.

### Claim 2 (depends on 1)

The semiconducting device of claim 1, wherein the graphene sheet forms a graphene bridge that spans the gap between the first contact and the second contact.

### Claim 3 (depends on 2)

The semiconducting device of claim 2, further comprising a gate material disposed on opposing faces of the graphene bridge in the gap.

### Claim 4 (depends on 3)

The semiconducting device of claim 3, further comprising a high-k dielectric material disposed on opposing faces of the graphene bridge between the graphene bridge and the gate material.

### Claim 5 (depends on 3)

The semiconducting device of claim 3, wherein a surface of the deposited gate material is coplanar with surfaces of the first contact and the second contact.

### Claim 6 (depends on 3)

The semiconducting device of claim 3, wherein a surface of the deposited gate material is recessed with respect to the top surfaces of the first contact and the second contact.

### Claim 7 (depends on 1)

The semiconducting device of claim 1, wherein the first contact and the second contact provide a self-aligned gate structure of the semiconducting device.

### Claim 8 (depends on 1)

The semiconducting device of claim 1, wherein the recess further comprises an anisotropically etched recess.

### Claim 9

A transistor, comprising:
a graphene sheet disposed directly on a substrate;
two or more contacts formed on the graphene sheet to define a gap between the two or more contacts;
at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet in the gap; and
a gate material in the gap defined by the one or more contacts, wherein the gate material fills a recess in the gap.

### Claim 10 (depends on 9)

The transistor of claim 9, wherein the graphene sheet forms a graphene bridge spanning the gap between the one or more contacts.

### Claim 11 (depends on 10)

The transistor of claim 10, wherein the gate material provides a dual gate structure with respect to the graphene bridge.

### Claim 12 (depends on 11)

The transistor of claim 11, further comprising a dielectric material disposed on opposing surfaces of the graphene bridge and between the graphene bridge and the gate material.

### Claim 13 (depends on 11)

The transistor of claim 11, wherein a surface of the gate material is coplanar with top surfaces of the one or more contacts.

### Claim 14 (depends on 11)

The transistor of claim 11, wherein a surface of the gate material is recessed with respect to the top surfaces of the one or more contacts.

### Claim 15 (depends on 9)

The transistor of claim 9, wherein the one or more contacts provide a self-aligned gate structure of the transistor.

### Claim 16

A self-aligned graphene transistor, comprising:
a graphene sheet disposed on a substrate of the graphene transistor;
a source contact on the substrate over the graphene sheet;
a drain contact on the substrate over the graphene sheet, wherein the drain contact is separated from the source contact by a gap;
at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and
a gate region in the gap that includes a recess formed by a passing the etchant through the graphene sheet to remove a portion of the substrate in the gap.

### Claim 17 (depends on 16)

The self-aligned graphene transistor of claim 16, wherein the graphene sheet forms a graphene bridge that spans the gap between the source contact and the drain contact.

### Claim 18 (depends on 17)

The self-aligned graphene transistor of claim 17, wherein the gate region include a gate material that fills the gap to surround the graphene bridge.

### Claim 19 (depends on 18)

The self-aligned graphene transistor of claim 18, further comprising a dielectric material forming a dual gate structure on opposing surfaces of the graphene bridge between the graphene bridge and the gate material.

### Claim 20 (depends on 16)

The self-aligned graphene transistor of claim 16, wherein the gate region is defined by anisotropic etching of the substrate in the gap.