# US 2014/0151641 A1 · 3d rfics with ultra-thin semiconductor materials

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- Number: US 2014/0151641 A1
- Document ID: US20140151641A1
- Status: Published application
- Kind: A1
- Application number: 13/705,845
- Filed: 2012-12-05
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Shu-Jen Han; Alberto Valdes Garcia
- Web page: https://patentgrep.com/patent/US20140151641A1

## CPC

- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 30/01: Manufacture or treatment
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 62/8303: {Diamond}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/01: {Manufacture or treatment}
- B82Y 30/00: Nanotechnology for materials or surface science, e.g. nanocomposites
- H10D 62/882: {Graphene}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Three-dimensional integrated circuits and method for fabricating the same include forming one or more passive components in a passive-layer dielectric; depositing additional dielectric material on the passive-layer dielectric; forming a gate structure in the additional dielectric material; forming a gate dielectric layer on the gate structure and the additional dielectric material; forming a thin channel material on the gate dielectric; forming source and drain regions in electrical contact with the thin channel material to form a transistor; and passivating the transistor and providing electrical access to the source and drain regions.

## Claims

### Claim 1

A method for forming a three-dimensional integrated circuit, comprising:
forming one or more passive components in a passive-layer dielectric;
monolithically forming additional dielectric material on the passive-layer dielectric;
forming a gate structure in the additional dielectric material;
forming a gate dielectric layer on the gate structure and the additional dielectric material;
forming a thin channel material on the gate dielectric;
forming source and drain regions in electrical contact with the thin channel material to form a transistor; and
passivating the transistor and providing electrical access to the source and drain regions.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming one or more surface components on a surface dielectric layer that is on a substrate;
monolithically forming the passive-layer dielectric material on the surface dielectric layer.

### Claim 3 (depends on 2)

The method of claim 2, further comprising etching the substrate to expose the one or more surface components.

### Claim 4 (depends on 1)

The method of claim 1, wherein the one or more surface components comprise an antenna.

### Claim 5 (depends on 1)

The method of claim 1, wherein the thin channel material is a graphene channel.

### Claim 6 (depends on 1)

The method of claim 1, wherein the thin channel material is formed from carbon nanotubes.

### Claim 7 (depends on 1)

The method of claim 1, wherein the steps of forming one or more passive components and depositing additional dielectric material are repeated at least once.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
forming a vertical interconnect via between passive components; and
depositing additional dielectric material on the passive-layer dielectric.

### Claim 9 (depends on 8)

The method of claim 8, wherein vertical interconnects are formed without the use of through-silicon vias.

### Claim 10

A method for forming a three-dimensional integrated circuit, comprising:
forming one or more surface components on a surface dielectric layer that is on a substrate;
monolithically forming a passive-layer dielectric material on the surface dielectric layer.
forming one or more passive components in the passive-layer dielectric;
monolithically forming additional dielectric material on the passive-layer dielectric;
forming a gate structure in the additional dielectric material;
forming a gate dielectric layer on the gate structure and the additional dielectric material;
forming a thin carbon-based channel material on the gate dielectric;
forming source and drain regions in electrical contact with the thin channel material to form a transistor;
passivating the transistor and providing electrical access to the source and drain regions; and
etching the substrate to expose the one or more surface components.

### Claim 11 (depends on 10)

The method of claim 10, wherein the one or more surface components comprise an antenna.

### Claim 12 (depends on 10)

The method of claim 10, wherein the thin channel material is a graphene channel.

### Claim 13 (depends on 10)

The method of claim 10, wherein the thin channel material is formed from carbon nanotubes.

### Claim 14 (depends on 10)

The method of claim 10, wherein the steps of forming one or more passive components and depositing additional dielectric material are repeated at least once.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
forming a vertical interconnect via between passive components; and
depositing additional dielectric material on the passive-layer dielectric.

### Claim at position 16

16-20. (canceled)