# US 2014/0151640 A1 · Self-aligned double-gate graphene transistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151640 A1 - Document ID: US20140151640A1 - Status: Published application - Kind: A1 - Application number: 13/693,700 - Filed: 2012-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Damon B. Farmer; Aaron D. Franklin; Joshua T. Smith - Web page: https://patentgrep.com/patent/US20140151640A1 ## CPC - H10D 62/882: {Graphene} - H10D 30/01: Manufacture or treatment - H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs} - H10D 30/021: {of FETs having insulated gates [IGFET]} - H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] - H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 48/01: Manufacture or treatment - H10D 62/8303: {Diamond} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10P 14/3406: {Carbon, e.g. diamond-like carbon} - Y10S 977/734: Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc. - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ## Abstract A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate. ## Claims ### Claim 1 A method of fabricating a semiconducting device, comprising: forming a graphene sheet on a substrate; forming a first contact and a second contact on the graphene sheet to define a gap between the first contact and the second contact; forming at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and applying the etchant to the substrate through the at least one slot formed in the graphene sheet to etch the substrate below the graphene sheet. ### Claim 2 (depends on 1) The method of claim 1, wherein etching the substrate forms a graphene bridge from the graphene sheet in the gap between the first contact and the second contact. ### Claim 3 (depends on 2) The method of claim 2, further comprising depositing a high-k dielectric material on the opposing faces of the graphene sheet via the at least one slot in the graphene sheet. ### Claim 4 (depends on 3) The method of claim 3, further comprising depositing a gate metal on opposed faces of the graphene sheet via the at least one slot in the graphene sheet to define a gate of the semiconducting device. ### Claim 5 (depends on 3) The method of claim 3, further comprising recessing a portion of the gate metal above the graphene bridge to a level below a top surface of the first contact and the second contact. ### Claim 6 (depends on 2) The method of claim 2, further comprising aligning the first contact and the second contact to provide a self-aligned gate structure of the semiconducting device. ### Claim 7 (depends on 1) The method of claim 1, wherein etching the substrate further comprises anisotropic etching of the substrate. ### Claim 8 A method of fabricating a transistor, comprising: forming a graphene sheet on a substrate; forming two or more contacts on the graphene sheet to define a gap between the two or more contacts; forming at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and removing a portion of the substrate in the gap via passing the etchant through the at least one slot. ### Claim 9 (depends on 8) The method of claim 8, further comprising removing the portion of the substrate in the gap to form a graphene bridge in the gap. ### Claim 10 (depends on 9) The method of claim 9, further comprising depositing a dielectric gate material on opposing faces of the graphene bridge via the at least one slot. ### Claim 11 (depends on 10) The method of claim 10, further comprising depositing a dielectric material on opposing faces of the graphene bridge via the at least one slot prior to depositing the gate material. ### Claim 12 (depends on 10) The method of claim 10, further comprising recessing a portion of the gate metal above the graphene bridge to a level below a top surface of the one or more contacts. ### Claim 13 (depends on 8) The method of claim 8, further comprising forming the one or more contacts to provide a self-aligned gate structure of the transistor. ### Claim 14 (depends on 8) The method of claim 8, wherein removing the substrate further comprises anisotropic etching of the substrate. ### Claim 15 A method of making a self-aligned graphene transistor, comprising: forming a graphene sheet on a substrate; forming a source contact on the graphene sheet; forming a drain contact on the graphene sheet, wherein the drain contact is separated from the source contact by a gap; forming at least one slot in the graphene sheet having a width that allows an etchant to pass through the graphene sheet; and removing a portion of the substrate in the gap between the source contact and the drain contact via passing the etchant through the at least one slot. ### Claim 16 (depends on 15) The method of claim 15, wherein removing the portion of the substrate in the gap between the source contact and the drain contact forms a graphene bridge in the gap. ### Claim 17 (depends on 16) The method of claim 16, further comprising depositing a dielectric gate material on opposing faces of the graphene bridge via the at least one slot. ### Claim 18 (depends on 17) The method of claim 17, further comprising depositing conformal high-k dielectric material annularly on the graphene bridge via the at least one slot. ### Claim 19 (depends on 15) The method of claim 15, wherein forming the source contact and the drain contact provides a self-aligned gate structure of the transistor. ### Claim 20 (depends on 15) The method of claim 15, wherein removing the portion of the substrate further comprises anisotropic etching of the substrate.