# US 2014/0151639 A1 · Nanomesh complementary metal-oxide-semiconductor field effect transistors

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- Number: US 2014/0151639 A1
- Document ID: US20140151639A1
- Status: Published application
- Kind: A1
- Application number: 13/692,188
- Filed: 2012-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: International Business Machines Corporation
- Inventors: Josephine B. Chang; Paul Chang; Michael A. Guillorn; Jeffrey W. Sleight
- Web page: https://patentgrep.com/patent/US20140151639A1

## CPC

- H10D 86/215: {comprising FinFETs}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/517: {characterised by the conducting layers}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack. A planarization dielectric layer and first and second gate cavities therein are subsequently formed. The first and second gate cavities are extended downward by etching the alternating stack employing a combination of the planarization layer and the fin-defining mask structures as an etch mask. The germanium-free silicon material is isotropically etched to laterally expand the first gate cavity and to form a first array of semiconductor nanowires including the silicon-germanium alloy, and the silicon-germanium alloy is isotropically etched to laterally expand the second gate cavity and to form a second array of semiconductor nanowires including the germanium-free silicon material. The first and second gate cavities are filled with replacement gate structures. Each replacement gate structure laterally can surround a two-dimensional array of semiconductor nanowires.

## Claims

### Claim 1

A method of forming a semiconductor structure comprising:
forming an alternating stack of a silicon-germanium alloy and a germanium-free silicon material on an insulator layer;
forming a planarization dielectric layer including a first gate cavity and a second gate cavity over said alternating stack;
forming a plurality of first semiconductor nanowires comprising one of said silicon-germanium alloy and said germanium-free silicon material underneath said first gate cavity by patterning a first portion of said alternating stack; and
forming a plurality of second semiconductor nanowires comprising another of said silicon-germanium alloy and said germanium-free silicon material underneath said second gate cavity by patterning a second portion of said alternating stack.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a plurality of fin-defining mask structures over said alternating stack prior to forming said planarization dielectric layer; and
extending said first gate cavity and said second gate cavity downward by etching said alternating stack employing a combination of said planarization dielectric layer and said plurality of fin-defining mask structures as an etch mask.

### Claim 3 (depends on 2)

The method of claim 2, wherein said patterning of said first portion of said alternating stack comprises laterally expanding said first gate cavity by removing said germanium-free silicon material selective to said silicon-germanium alloy while an etch-resistant material portion masks said second portion of said alternating stack.

### Claim 4 (depends on 3)

The method of claim 3, wherein said lateral expansion of said first gate cavity is performed by an isotropic etch, and said etch-resistant material portion is a photoresist portion.

### Claim 5 (depends on 3)

The method of claim 3, further comprising forming p-n junctions within said first portion of said alternating stack, wherein said forming of said plurality of first semiconductor nanowires comprises removing portion of said germanium-free silicon material to physically expose portions of said p-n junctions within said silicon-germanium alloy.

### Claim 6 (depends on 3)

The method of claim 3, wherein said patterning of said second portion of said alternating stack comprises laterally expanding said second gate cavity by removing said silicon-germanium alloy selective to said germanium-free silicon material while another etch-resistant material portion masks said second portion of said alternating stack.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming a first disposable gate structure over said first portion of said alternating stack and a second disposable gate structure over said second portion of said alternating stack;
depositing and planarizing a dielectric material over said first and second disposable gate structures; and
removing said first and second disposable gate structures selective to said deposited and planarized dielectric material, wherein said deposited and planarized dielectric material constitutes said planarization dielectric layer including said first gate cavity and said second gate cavity.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
forming a plurality of fin-defining mask structures over said alternating stack, wherein said first and second disposable gate structures are formed over said plurality of fin-defining mask structures; and
extending said first gate cavity and said second gate cavity downward by etching said alternating stack employing a combination of said planarization dielectric layer and said plurality of fin-defining mask structures as an etch mask.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
providing a dopant of a first conductivity type to said first portion of said alternating stack prior to said forming of said planarization dielectric layer; and
providing a dopant of a second conductivity type that is the opposite of said first conductivity type to said second portion of said alternating stack.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a first disposable gate structure over said first portion of said alternating stack and a second disposable gate structure over said second portion of said alternating stack;
doping sub-portions of said first portion of said alternating stack with dopants of said second conductivity type employing said first disposable gate structure as an implantation mask; and
doping sub-portions of said second portion of said alternating stack with dopants of said first conductivity type employing said second disposable gate structure as an implantation mask.

### Claim 11 (depends on 10)

The method of claim 10, wherein said sub-portions of said first portion of said alternating stack comprises:
a first source region comprising a first portion of said alternating stack; and
a first drain region comprising a second portion of said alternating stack, and said sub-portions of said second portion of said alternating stack comprises:
a second source region comprising a third portion of said alternating stack; and
a second drain region comprising a fourth portion of said alternating stack.

### Claim 12 (depends on 1)

The method of claim 1, wherein an entirety of said alternating stack is single crystalline upon formation.

### Claim 13

A semiconductor structure comprising a first field effect transistor and a second field effect transistor,
wherein said first field effect transistor comprises:
a first source region comprising a first alternating stack of a silicon-germanium alloy and a germanium-free silicon material;
a first drain region comprising a second alternating stack of said silicon-germanium alloy and said germanium-free silicon material;
a plurality of first channels located within a plurality of first semiconductor nanowires comprising said silicon-germanium alloy and extending between said first source region and said first drain region; and
a first gate electrode surrounding each of said first plurality of semiconductor nanowires, and wherein said second field effect transistor comprises:
a second source region comprising a third alternating stack of said silicon-germanium alloy and said germanium-free silicon material;
a second drain region comprising a fourth alternating stack of said silicon-germanium alloy and said germanium-free silicon material;
a plurality of second channels located within a plurality of second semiconductor nanowires comprising said germanium-free silicon material and extending between said second source region and said second drain region; and
a second gate electrode surrounding each of said second plurality of semiconductor nanowires.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein said first source region, said first drain region, said second source region, and said second drain region are in contact with an insulator layer.

### Claim 15 (depends on 13)

The semiconductor structure of claim 13, wherein said first source region, said first drain region, said second source region, and said second drain region are single crystalline.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein said germanium-free silicon material consists essentially of silicon and optional dopants of p-type or n-type.

### Claim 17 (depends on 15)

The semiconductor structure of claim 15, wherein said plurality of first semiconductor nanowires is under a first type of strain along a lengthwise direction of said plurality of first semiconductor nanowires, and said plurality of second semiconductor nanowires is under a second type of strain along a lengthwise direction of said plurality of second semiconductor nanowires, wherein one of said first type and said second type is compressive, and another of said first type and said second type is tensile.

### Claim 18 (depends on 14)

The semiconductor structure of claim 14, wherein each of said plurality of first channels and said plurality of second channels comprises an intrinsic semiconductor material.

### Claim 19 (depends on 13)

The semiconductor structure of claim 13, wherein said first source region comprises first end portions of said plurality of first semiconductor nanowires, said first drain region comprises second end portions of said plurality of first semiconductor nanowires, said second source region comprises first end portions of said plurality of second semiconductor nanowires, and said second drain region comprises second end portions of said plurality of second semiconductor nanowires.

### Claim 20 (depends on 19)

The semiconductor structure of claim 19, further comprising:
a first gate spacer comprising a dielectric material and contacting a sidewall of said first source region and a sidewall of said first drain region; and
a second gate spacer comprising said dielectric material and contacting a sidewall of said second source region and a sidewall of said second drain region.

### Claim 21 (depends on 20)

The semiconductor structure of claim 20, wherein said first gate spacer comprises at least one vertical strip having a uniform width and contacting sidewalls of at least two of said plurality of first semiconductor nanowires, and said second gate spacer comprises at least one vertical strip having said uniform width and contacting sidewalls of at least two of said plurality of second semiconductor nanowires.

### Claim 22 (depends on 21)

The semiconductor structure of claim 21, wherein said first source region, said first drain region, said second source region, and said second drain region are in contact with an insulator layer, and said first and second gate spacers are in contact with said insulator layer.

### Claim 23 (depends on 20)

The semiconductor structure of claim 20, further comprising a planarization dielectric layer located over said first source region, said first drain region, said second source region, and said second drain region and contacting sidewalls of said first and second gate spacers.

### Claim 24 (depends on 23)

The semiconductor structure of claim 23, wherein a top surface of said first gate electrode and a top surface of said second gate electrode are coplanar with a top surface of said planarization dielectric layer.

### Claim 25 (depends on 20)

The semiconductor structure of claim 20, wherein said first gate electrode includes a plurality of portions that laterally extend underneath said first gate spacer along a lengthwise direction of said plurality of first semiconductor fins, and said second gate electrode includes a plurality of portions that laterally extend underneath said second gate spacer along a lengthwise direction of said plurality of second semiconductor fins.