# US 2014/0151627 A1 · Semiconductor device and method of manufacturing the same

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- Number: US 2014/0151627 A1
- Document ID: US20140151627A1
- Status: Published application
- Kind: A1
- Application number: 13/830,721
- Filed: 2013-03-14
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: SK hynix Inc.
- Applicants: SK Hynix Inc.
- Inventors: Young Ok HONG; Kyoung A KIM
- Web page: https://patentgrep.com/patent/US20140151627A1

## CPC

- H10N 70/821: {Device geometry}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 70/25: {based on bulk electronic defects, e.g. trapping of electrons}
- H10N 70/883: {Oxides or nitrides}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Disclosed is a semiconductor device and a method of manufacturing the same. The semiconductor device includes first material layers and second material layers alternately stacked on a first conductive layer. Through holes, each through holes including a first through region, second through region and trench, wherein the first and second through regions pass through the first and second material layers, and the trench is formed in the first conductive layer to connect the first through region and the second through region. Resistive layers, each resistive layer including a first region are disposed in the first through region, a second region disposed in the second through region, and a third region disposed in the trench.

## Claims

### Claim 1

A semiconductor device, comprising:
first material layers and second material layers alternately stacked on a first conductive layer;
through holes, each through hole including a first through region, a second through region and a trench, wherein the first and second through regions pass through the first and second material layers, and the trench is formed in the first conductive layer to connect the first and second through regions; and
resistive layers, each resistive layer including a first region disposed in the first through egion, a second region disposed in the second through region, and a third region disposed in the trench.

### Claim 2

The semiconductor device of claim further comprising:
a first pad pattern connected to the first region of each of the resistive layers; and
a second pad pattern connected to the second region of each of the resistive layers.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first pad pattern connected to a first resistive layer among the resistive layers;
a second pad pattern connected to a second resistive layer among the resistive layers; and
a conductive pattern connecting the first resistive layer and the second resistive layer in series.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first pad pattern connected to the second region of a first resistive layer among the resistive layers and the first region of a second resistive layer among the resistive layers; and
a second pad pattern connected to the first region of the first resistive layer and the second region of the second resistive layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
interlayer insulation patterns formed in substantially the same planes as the first material layers;
third conductive patterns formed in substantially the same planes as the second material layers;
a first channel layer and a second channel layer passing through the interlayer insulation patterns and the third conductive patterns;
a pipe channel layer to connect the first and second channel layers; and
a pipe gate to surround the pipe channel layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the interlayer insulation patterns are formed of the same material as that of the first material layers.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the third conductive patterns are formed of the same material as that of the second material layers.

### Claim 8 (depends on 5)

The semiconductor device of claim 5, wherein the interlayer insulation patterns are formed of a different material than that of the first material layers.

### Claim 9 (depends on 5)

The semiconductor device of claim 5, wherein the third conductive patterns are formed of a different material than that of the second material layers.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising:
a thin film formed along an interface between each of the resistive layers and each of the through holes.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the thin film includes at least one of a charge blocking layer, a data storage layer, and a tunnel insulation layer.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein each of the resistive layers fills each of the through holes.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein each of the resistive layers is formed along a surface defining each of the through holes so that each of the resistive layers has a tubular shape with an open central portion.

### Claim 14

The semiconductor device of claim further comprising:
a fourth conductive layer formed on the first conductive layer.

### Claim 15

A method of manufacturing a semiconductor device, the method comprising:
forming a conductive layer on a resistor region of a substrate including a cell array region and the resistor region;
forming trenches by etching the conductive layer;
forming sacrificial layers in the trenches;
alternately stacking first material layers and second material layers on the conductive layer and the sacrificial layers;
forming first through regions and second through regions through the first material layers and the second material layers to expose the sacrificial layers;
removing the sacrificial layers; and
forming resistive layers, each resistive layer including a first region, a second region and a third region, wherein the first region is disposed in each of the first throuoh regions, the second through region is disposed in each of the second through regions, and a third region is disposed in each of the trenches.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming a first pad pattern and a second pad pattern on the first material layers and the second material layers,
wherein the first and second patterns are connected to theist and second regions of each of the resistive layers, respectively.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
forming a first pad pattern, a second pad pattern, and a conductive pattern,
wherein the first pad pattern is connected to a first resistive layer of the resistive layers, and the second pad pattern is connected to a second resistive layer of the resistive layers, and the conductive pattern connects the first resistive layer and the second resistive layer.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
forming a first pad pattern connected to the second region of a first resistive layer among the resistive layers and the first region of a second resistive layer among the resistive layers; and
forming a second pad pattern connected to the first region of the first resistive layer and the second region of the second resistive layer.