# US 2014/0151626 A1 · Selector Device Using Low Leakage Dielectric Mimcap Diode > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151626 A1 - Document ID: US20140151626A1 - Status: Published application - Kind: A1 - Application number: 13/693,820 - Filed: 2012-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: Intermolecular, Inc. - Applicants: Intermolecular Inc. - Inventors: Prashant B. Phatak - Web page: https://patentgrep.com/patent/US20140151626A1 ## CPC - H10D 1/692: {Electrodes} - H10B 63/22: {of the metal-insulator-metal type} - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10N 70/00: Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching (integrated devices or assemblies of multiple devices H10N79/00) - H10P 14/40: of conductive or resistive materials - H10P 14/416: {of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers} - H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD} - H10P 14/6519: {the substance being oxygen} - H10P 14/6532: {by exposure to a plasma} - H10P 14/69215: {the material being a silicon oxide, e.g. SiO2} - H10P 14/69391: {the material containing aluminium, e.g. Al2O3} - H10P 14/69392: {the material containing hafnium, e.g. HfO2} - H10P 14/69394: {the material containing titanium, e.g. TiO2} - H10P 14/69395: {the material containing zirconium, e.g. ZrO2} - H10P 14/69396: {the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium} - H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz} - H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/8833: {Binary metal oxides, e.g. TaOx} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes. ## Claims ### Claim 1 A device comprising a first layer, wherein the first layer is operable as a first electrode; a second layer disposed above the first layer, wherein the second layer comprises a dielectric layer; a third layer disposed above the first layer, wherein the third layer comprises a dielectric layer, wherein the second layer has a different band gap than the third layer; a fourth layer disposed above the first layer, wherein the fourth layer comprises a dielectric layer, wherein the leakage current of the fourth layer is higher than that of the third layer; a fifth layer disposed above the first layer, wherein the fifth layer is operable as a second electrode; wherein the second, third and fourth layers are operable to have a higher current flow when biased in a first polarity and a lower current flow when biased in a second polarity; wherein the second polarity is opposite of the first polarity. ### Claim 2 (depends on 1) A device as in claim 1 wherein the first layer or the fifth layer comprises at least one of TiN, Ti, Al, MoO2, W, poly-Si, TiSiN, TaSiN, or Ni. ### Claim 3 (depends on 1) A device as in claim 1 wherein the second layer comprises at least one of AlOx, AlN, doped ZrOx or HfOx, SiO2, or SiN. ### Claim 4 (depends on 1) A device as in claim 1 wherein the thickness of the second layer is between 1 and 3 nm. ### Claim 5 (depends on 1) A device as in claim 1 wherein the third layer comprises at least one of ZrOx, HfOx, doped ZrOx, or doped HfOx. ### Claim 6 (depends on 1) A device as in claim 1 wherein the fourth layer comprises at least one of ZrOx, HfOx, TiOx, NbOx, or ZnO. ### Claim 7 (depends on 1) A device as in claim 1 wherein the thickness of the third or fourth layer is between 3 and 10 nm. ### Claim 8 (depends on 1) A device as in claim 1 wherein one of the second layer is disposed on the third layer, which is disposed on the fourth layer, and wherein the second, third and fourth layers are sandwiched between the first and fifth layer; the second layer is disposed on the fourth layer, which is disposed on the third layer, and wherein the second, third and fourth layers are sandwiched between the first and fifth layer; the third layer is disposed on the fourth layer, which is disposed on the second layer, and wherein the second, third and fourth layers are sandwiched between the first and fifth layer; or the fourth layer is disposed on the third layer, which is disposed on the second layer, and wherein the second, third and fourth layers are sandwiched between the first and fifth layer. ### Claim 9 A memory array comprising a first plurality of conductive lines; a second plurality of conductive lines, wherein the second plurality of conductive lines is forming an angle with the first plurality of conductive lines; a plurality of elements disposed at the cross points of the first and second plurality of conductive lines, wherein each element comprises a first layer, wherein the first layer is operable as a first electrode; a second layer disposed above the first layer, wherein the second layer comprises a dielectric layer; a third layer disposed above the first layer, wherein the third layer comprises a dielectric layer, wherein the second layer has a different band gap than the third layer; a fourth layer disposed above the first layer, wherein the fourth layer comprises a dielectric layer, wherein the leakage current of the fourth layer is higher than that of the third layer; a fifth layer disposed above the first layer, wherein the fifth layer is operable as a second electrode; wherein the second, third and fourth layers are operable to have a higher current flow when biased in a first polarity and a lower current flow when biased in a second polarity; wherein the second polarity is opposite of the first polarity; a resistive switching memory element disposed above the fifth layer; a sixth layer disposed above the first layer, wherein the sixth layer is operable as a third electrode. ### Claim 10 (depends on 1) A memory array as in claim 1 wherein the first layer or the fifth layer comprises at least one of TiN, Ti, Al, MoO2, W, poly-Si, TiSiN, TaSiN, or Ni. ### Claim 11 (depends on 1) A memory array as in claim 1 wherein the second layer comprises at least one of AlOx, AlN, doped ZrOx or HfOx, SiO2, or SiN. ### Claim 12 (depends on 1) A memory array as in claim 1 wherein the thickness of the second layer is between 1 and 3 nm. ### Claim 13 (depends on 1) A memory array as in claim 1 wherein the third layer comprises at least one of ZrOx, HfOx, doped ZrOx, or doped HfOx. ### Claim 14 (depends on 1) A memory array as in claim 1 wherein the fourth layer comprises at least one of ZrOx, HfOx, TiOx, NbOx, or ZnO. ### Claim 15 (depends on 1) A memory array as in claim 1 wherein the thickness of the third or the fourth layer is between 3 and 10 nm. ### Claim 16 A method to form a device, the method comprising forming a first layer, wherein the first layer is operable as an electrode; forming a second layer disposed above the first layer, wherein the second layer comprises a dielectric layer; forming a third layer disposed above the first layer, wherein the third layer comprises a dielectric layer, wherein the second layer has a different band gap than the third layer; forming a fourth layer disposed above the first layer, wherein the fourth layer comprises a dielectric layer, wherein the leakage current of the fourth layer is higher than that of the third layer; forming a fifth layer disposed above the first layer, wherein the fifth layer is operable as an electrode; wherein the second, third and fourth layers are operable to have a higher current flow when biased in a first polarity and a lower current flow when biased in a second polarity; wherein the second polarity is opposite of the first polarity. ### Claim 17 (depends on 16) A method as in claim 16 wherein one of the second layer is disposed on the third layer, which is disposed on the fourth layer, and wherein the second, third and fourth layers are sandwiched between the first and fifth layer; the second layer is disposed on the fourth layer, which is disposed on the third layer, and wherein the second, third and fourth layers are sandwiched between the first and fifth layer; the third layer is disposed on the fourth layer, which is disposed on the second layer, and wherein the second, third and fourth layers are sandwiched between the first and fifth layer; or the fourth layer is disposed on the third layer, which is disposed on the second layer, and wherein the second, third and fourth layers are sandwiched between the first and fifth layer. ### Claim 18 (depends on 16) A method as in claim 16 further comprising performing a treatment after forming the second, third, fourth, or fifth layer. ### Claim 19 (depends on 18) A method as in claim 18 wherein the treatment comprises a rapid thermal oxidation process. ### Claim 20 (depends on 18) A method as in claim 18 wherein the treatment comprises a plasma annealing process in an oxygen ambient.