# US 2014/0151455 A1 · Radio frequency identification (rfid) tag and manufacturing methods thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151455 A1 - Document ID: US20140151455A1 - Status: Published application - Kind: A1 - Application number: 13/884,969 - Filed: 2011-03-14 - Published: 2014-06-05 - Earliest claimed: 2011-01-28 - Assignees: Shanghai Ic R&D Center Co., Ltd - Inventors: Chen Li; Yong Wang; Shoumian Chen - Web page: https://patentgrep.com/patent/US20140151455A1 ## CPC - G06K 19/07771: {the record carrier comprising means for minimising adverse effects on the data communication capability of the record carrier, e.g. minimising Eddy currents induced in a proximate metal or otherwise electromagnetically interfering object} - G06K 19/0775: {arrangements for connecting the integrated circuit to the antenna} - G06K 19/07775: {the antenna being on-chip} - G06K: GRAPHICAL DATA READING (image or video recognition or understanding G06V); PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS ## Abstract A radio frequency identification (RFID) device is disclosed. The RFID device includes a silicon substrate having a top side and a bottom side. The RFID device also includes a plurality of circuitry layers formed on the top side of the substrate, and the plurality of circuitry layers include at least a core circuitry and an on-chip antenna. Further, the RFID device includes a plurality of deep openings formed in the substrate on the bottom side under the plurality of circuitry layers. The plurality of deep openings are arranged in an array and through a substantial portion of the substrate, and a remaining portion of the substrate unreached by the plurality of deep openings separates the plurality of deep openings and the plurality of circuitry layers. ## Claims ### Claim 1 A radio frequency identification (RFID) device, comprising: a silicon substrate having a top side and a bottom side; a plurality of circuitry layers formed on the top side of the substrate, wherein the plurality of circuitry layers include at least a core circuitry and an on-chip antenna; and a plurality of deep openings formed in the substrate on the bottom side under the plurality of circuitry layers, wherein the plurality of deep openings are arranged in an array and through a substantial portion of the substrate, wherein a remaining portion of the substrate unreached by the plurality of deep openings separates the plurality of deep openings and the plurality of circuitry layers. ### Claim 2 (depends on 1) The RFID device according to claim 1, wherein: the plurality of deep openings are formed under the on-chip antenna, and an area containing the plurality of deep openings correspond to an area of the on-chip antenna. ### Claim 3 (depends on 2) The RFID device according to claim 2, wherein: the core circuitry does not overlap with the on-chip antenna. ### Claim 4 (depends on 1) The RFID device according to claim 1, wherein: the on-chip antenna connects with the core circuitry and is wound around the core circuitry, and a total number of turns is determined by a frequency operated by the RFID device. ### Claim 5 (depends on 1) The RFID device according to claim 1, wherein: the plurality of deep openings are formed using at least one of an inductively coupled plasma (ICP) etching method and a reactive ion etching (RIE) method. ### Claim 6 (depends on 1) The RFID device according to claim 1, wherein: a thickness of the remaining portion of the substrate is in a range of approximately 1 μm-40 μm. ### Claim 7 (depends on 6) The RFID device according to claim 6, wherein: the thickness of the remaining portion of the substrate is approximately 5 μm. ### Claim 8 (depends on 1) The RFID device according to claim 1, wherein: a diameter of each of the plurality of deep openings is in a range of approximately 1 μm-10 μm. ### Claim 9 (depends on 8) The RFID device according to claim 8, wherein: the diameter of each of the plurality of deep openings is approximately 5 μm. ### Claim 10 (depends on 1) The RFID device according to claim 1, wherein: spacing among the plurality of deep openings is in a range of approximately 1 μm-10 μm. ### Claim 11 (depends on 10) The RFID device according to claim 10, wherein: the spacing among the plurality of deep openings is approximately 5 μm. ### Claim 12 A method for making a radio frequency identification (RFID) device, comprising: providing a silicon substrate having a top side and a bottom side; fabricating a plurality of circuitry layers including a core circuitry and an on-chip antenna on the top side of the substrate using standard CMOS processes; forming a plurality of deep openings in the substrate on the bottom side under the plurality of circuitry layers after the plurality of circuitry layers were fabricated, wherein the plurality of deep openings are arranged in an array and through a substantial portion of the substrate; and separating the plurality of deep openings and the plurality of circuitry layers by a remaining portion of the substrate unreached by the plurality of deep openings. ### Claim 13 (depends on 12) The method according to claim 12, wherein forming the deep openings further includes: forming the plurality of deep openings under the on-chip antenna in an area corresponding to an area of the on-chip antenna. ### Claim 14 (depends on 12) The method according to claim 12, wherein forming the deep openings further includes: forming the plurality of deep openings using at least one of an inductively coupled plasma (ICP) etching method and a reactive ion etching (RIE) method. ### Claim 15 (depends on 14) The method according to claim 14, further including: controlling a thickness of the remaining portion of the substrate in a range of approximately 1 μm-40 μm based on an etching rate of the substrate. ### Claim 16 (depends on 15) The method according to claim 15, wherein: the thickness of the remaining portion of the substrate is approximately 5 μm. ### Claim 17 (depends on 12) The method according to claim 12, wherein: a diameter of each of the plurality of deep openings is in a range of approximately 1 μm-10 μm. ### Claim 18 (depends on 17) The method according to claim 17, wherein: the diameter of each of the plurality of deep openings is approximately 5 μm. ### Claim 19 (depends on 12) The method according to claim 12, wherein: spacing among the plurality of deep openings is in a range of approximately 1 μm-10 μm. ### Claim 20 (depends on 19) The method according to claim 19, wherein: the spacing among the plurality of deep openings is approximately 5 μm. ### Claim 21 A method for making a radio frequency identification (RFID) device, comprising: providing a silicon substrate having a top side and a bottom side; forming a plurality of deep openings in the substrate on the bottom side, wherein the plurality of deep openings are arranged in an array and through a substantial portion of the substrate; fabricating a plurality of circuitry layers including a core circuitry and an on-chip antenna on the top side of the substrate above the plurality of deep openings, after the plurality of deep openings were formed, using standard CMOS processes; and separating the plurality of deep openings and the plurality of circuitry layers by a remaining portion of the substrate unreached by the plurality of deep openings. ### Claim 22 (depends on 21) The method according to claim 21, wherein forming the deep openings further includes: forming the plurality of deep openings in an area on the bottom side of the substrate corresponding to an area of the on-chip antenna. ### Claim 23 (depends on 21) The method according to claim 21, wherein forming the deep openings further includes: forming the plurality of deep openings using at least one of an inductively coupled plasma (ICP) etching method and a reactive ion etching (RIE) method. ### Claim 24 (depends on 21) The method according to claim 21, further including: controlling a thickness of the remaining portion of the substrate in a range of approximately 1 μm-40 μm based on an etching rate of the substrate. ### Claim 25 (depends on 24) The method according to claim 24, wherein: the thickness of the remaining portion of the substrate is approximately 5 μm. ### Claim 26 (depends on 21) The method according to claim 21, wherein: a diameter of each of the plurality of deep openings is in a range of approximately 1 μm-10 μm. ### Claim 27 (depends on 26) The method according to claim 26, wherein: the diameter of each of the plurality of deep openings is approximately 5 μm. ### Claim 28 (depends on 21) The method according to claim 21, wherein: spacing among the plurality of deep openings is in a range of approximately 1 μm-10 μm. ### Claim 29 (depends on 28) The method according to claim 28, wherein: the spacing among the plurality of deep openings is approximately 5 μm.