# US 2014/0151104 A1 · Electronic component embedded substrate and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151104 A1 - Document ID: US20140151104A1 - Status: Published application - Kind: A1 - Application number: 14/090,469 - Filed: 2013-11-26 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: Samsung Electro-Mechanics Co., Ltd. - Applicants: Samsung Electro-Mechanics Co., Ltd. - Inventors: Yul Kyo CHUNG; DOO HWAN LEE; SEUNG EUN LEE; YEE NA SHIN - Web page: https://patentgrep.com/patent/US20140151104A1 ## CPC - H05K 1/186: {manufactured by mounting on or connecting to patterned circuits before or during embedding} - H05K 3/403: {Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof (H05K3/4092 takes precedence)} - H05K 3/4602: {characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated} - H05K 2201/09645: Patterning on via walls; Plural lands around one hole - H05K 2203/0228: Cutting, sawing, milling or shearing - H05K 2203/0242: Cutting around hole, e.g. for disconnecting land or Plated Through-Hole [PTH] or for partly removing a PTH - Y10T 29/49139: by inserting component lead or terminal into base aperture - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract The present invention relates to an electronic component embedded substrate including: a cavity formed in at least one insulating layer provided inside the electronic component embedded substrate; an electronic component having at least a portion inserted in the cavity; and a cavity plating portion formed on a surface of the cavity opposite to at least one surface of the electronic component, and can improve electrical connectivity between an external electrode and a via even when the size of the external electrode of the electronic component is reduced than before. ## Claims ### Claim 1 An electronic component embedded substrate having an electronic component embedded therein, comprising: a cavity formed in at least one insulating layer provided inside the electronic component embedded substrate; an electronic component having at least a portion inserted in the cavity; and a cavity plating portion formed on a surface of the cavity opposite to at least one surface of the electronic component. ### Claim 2 (depends on 1) The electronic component embedded substrate according to claim 1, wherein an external electrode is provided on a side surface of the electronic component, and further comprising: a conductive filling portion formed by filling a conductive material between the cavity plating portion and the external electrode to electrically connect between the cavity plating portion and the external electrode. ### Claim 3 (depends on 2) The electronic component embedded substrate according to claim 2, further comprising: a via having one surface in contact with at least one area selected from at least a portion of the external electrode, at least a portion of the conductive filling portion, and at least a portion of the cavity plating portion. ### Claim 4 (depends on 3) The electronic component embedded substrate according to claim 3, wherein the external electrode consists of at least two electrodes provided on a surface of the electronic component to be separated from each other, disconnecting portions are formed in the cavity plating portion connected to the electrodes to electrically isolate the electrodes from each other, and a conductive filling portion is filled between the respective cavity plating portions and the respective electrodes electrically separated by the disconnecting portions. ### Claim 5 (depends on 4) The electronic component embedded substrate according to claim 4, wherein an insulating material is filled in a space between the electrodes, between the disconnecting portions, and between the conductive filling portions. ### Claim 6 (depends on 2) The electronic component embedded substrate according to claim 2, further comprising: a metal pattern provided on a surface of the insulating layer and electrically connected to the cavity plating portion; and a via having one surface in contact with at least one area selected from at least a portion of the external electrode, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the metal pattern. ### Claim 7 (depends on 6) The electronic component embedded substrate according to claim 6, wherein the external electrode consists of at least two electrodes provided on a surface of the electronic component to be separated from each other, disconnecting portions are formed in the cavity plating portion connected to the electrodes to electrically isolate the electrodes from each other, and a conductive filling portion is filled between the respective cavity plating portions and the respective electrodes electrically separated by the disconnecting portions. ### Claim 8 (depends on 7) The electronic component embedded substrate according to claim 7, wherein an insulating material is filled in a space between the electrodes, between the disconnecting portions, and between the conductive filling portions. ### Claim 9 (depends on 2) The electronic component embedded substrate according to claim 2, wherein a plurality of electronic components are inserted in the cavity, and at least two of the plurality of electronic components are connected in parallel. ### Claim 10 (depends on 1) The electronic component embedded substrate according to claim 1, wherein an external electrode is provided on a side surface of the electronic component, and the cavity plating portion and the external electrode are in contact with each other to be electrically connected to each other. ### Claim 11 (depends on 10) The electronic component embedded substrate according to claim 10, further comprising: a via having one surface in contact with at least one area selected from at least a portion of the external electrode and at least a portion of the cavity plating portion. ### Claim 12 (depends on 11) The electronic component embedded substrate according to claim 11, wherein the external electrode consists of at least two electrodes provided on a surface of the electronic component to be separated from each other, and disconnecting portions are formed in the cavity plating portion connected to the electrodes to electrically isolate the electrodes from each other. ### Claim 13 (depends on 12) The electronic component embedded substrate according to claim 12, wherein an insulating material is filled in a space between the electrodes and between the disconnecting portions. ### Claim 14 (depends on 10) The electronic component embedded substrate according to claim 10, further comprising: a metal pattern provided on a surface of the insulating layer and electrically connected to the cavity plating portion; and a via having one surface in contact with at least one area selected from at least a portion of the external electrode, at least a portion of the cavity plating portion, and at least a portion of the metal pattern. ### Claim 15 (depends on 14) The electronic component embedded substrate according to claim 14, wherein the external electrode consists of at least two electrodes provided on a surface of the electronic component to be separated from each other, and disconnecting portions are formed in the cavity plating portion connected to the electrodes to electrically isolate the electrodes from each other. ### Claim 16 (depends on 15) The electronic component embedded substrate according to claim 15, wherein an insulating material is filled in a space between the electrodes and between the disconnecting portions. ### Claim 17 (depends on 10) The electronic component embedded substrate according to claim 10, wherein a plurality of electronic components are inserted in the cavity, and at least two of the plurality of electronic components are connected in parallel. ### Claim 18 An electronic component embedded substrate in which an electronic component comprising a hexahedral body portion and two external electrodes which cover opposite surfaces of the body portion is embedded, comprising: a cavity formed in at least one insulating layer provided inside the electronic component embedded substrate; and a cavity plating portion formed on a surface of the cavity opposite to the external electrode. ### Claim 19 An electronic component embedded substrate comprising: a first insulating layer having a first metal pattern on a lower surface and a second metal pattern on an upper surface and comprising a cavity passing through the upper surface and the lower surface; an electronic component having at least one external electrode on a surface and having at least a portion inserted in the cavity; a cavity plating portion formed on a surface of the cavity opposite to the external electrode to be electrically connected to at least one of the first metal pattern and the second metal pattern; a conductive filling portion formed by filling a conductive material between the cavity plating portion and the external electrode; a second insulating layer for covering exposed surfaces of the first metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component; a first circuit pattern formed on a surface of the second insulating layer; and a via having one surface in contact with at least one area selected from at least a portion of the external electrode, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the first metal pattern portion in contact with the cavity plating portion, and the other surface in contact with the first circuit pattern. ### Claim 20 (depends on 19) The electronic component embedded substrate according to claim 19, wherein the electronic component has at least two external electrodes formed in separated areas on a surface of the electronic component, disconnecting portions are formed in the cavity plating portion connected to the external electrodes to electrically isolate the electrodes from each other, and the conductive filling portion is filled between the respective cavity plating portions and the respective external electrodes electrically separated by the disconnecting portions. ### Claim 21 (depends on 20) The electronic component embedded substrate according to claim 20, wherein a material of the second insulating layer is filled in a space between the external electrodes, between the disconnecting portions, and between the conductive filling portions. ### Claim 22 (depends on 20) The electronic component embedded substrate according to claim 20, further comprising: a fifth via having one surface in contact with at least a portion of the first metal pattern except the portion in contact with the cavity plating portion, and the other surface in contact with at least a portion of the first circuit pattern. ### Claim 23 (depends on 20) The electronic component embedded substrate according to claim 20, further comprising: a third insulating layer for covering the exposed surfaces of the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component; a second circuit pattern formed on a surface of the third insulating layer; and a third via having one surface in contact with at least one area selected from at least a portion of the external electrode, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the second metal pattern portion in contact with the cavity plating portion, and the other surface in contact with the second circuit pattern. ### Claim 24 (depends on 23) The electronic component embedded substrate according to claim 23, wherein at least one of a material of the first insulating layer and a material of the second insulating layer is filled in a space between the external electrodes, between the disconnecting portions, and between the conductive filling portions. ### Claim 25 (depends on 23) The electronic component embedded substrate according to claim 23, further comprising: a sixth via having one surface in contact with at least a portion of the second metal pattern except the portion in contact with the cavity plating portion, and the other surface in contact with at least a portion of the second circuit pattern. ### Claim 26 A method of manufacturing an electronic component embedded substrate having an electronic component embedded therein, comprising: forming a cavity in at least one insulating layer provided inside the electronic component embedded substrate and forming a cavity plating portion by plating a conductive material on a surface of the cavity; and inserting at least a portion of the electronic component in the cavity. ### Claim 27 (depends on 26) The method of manufacturing an electronic component embedded substrate according to claim 26, further comprising, after the inserting, filling a conductive material in a space between the electronic component and the cavity plating portion. ### Claim 28 (depends on 26) The method of manufacturing an electronic component embedded substrate according to claim 26, wherein the forming a cavity comprises: forming a temporary remaining portion in a portion of the area in which the cavity is to be formed by processing a first temporary cavity having a “⊂” shape and a second temporary cavity having a shape symmetrical to the first temporary cavity to face each other while being separated from each other by a predetermined interval; plating a conductive material on surfaces of the first temporary cavity and the second temporary cavity; and removing the temporary remaining portion. ### Claim 29 (depends on 26) The method of manufacturing an electronic component embedded substrate according to claim 26, wherein the forming a cavity comprises: forming a third temporary cavity in an area except a first projecting portion formed by projecting the insulating layer in the direction of a surface facing one surface of the cavity and a second projecting portion formed to be symmetrical to the first projecting portion on a surface facing the surface on which the first projecting portion is formed; plating a conductive material on a surface of the third temporary cavity; and removing portions of the first projecting portion and the second projecting portion. ### Claim 30 A method of manufacturing an electronic component embedded substrate, comprising: providing a first insulating layer having a first metal pattern on a lower surface and a second metal pattern on an upper surface; forming a cavity in the first insulating layer and forming a cavity plating portion electrically connected to at least one of the first metal pattern and the second metal pattern by plating a conductive material on a surface of the cavity; attaching a detach film to a lower surface of the first metal pattern; attaching a lower surface of an electronic component to the detach film by inserting at least a portion of the electronic component having a plurality of external electrodes on a surface; forming a conductive filling portion by filling a conductive material between the cavity plating portion and the external electrodes; forming a third insulating layer by applying an insulating material on exposed surfaces of the second metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component; processing a via hole, which exposes at least one area selected from at least a portion of the external electrodes, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the second metal pattern portion in contact with the cavity plating portion, through the third insulating layer; and filling a conductive material in the via hole and forming a second circuit pattern on an upper surface of the third insulating layer. ### Claim 31 (depends on 30) The method of manufacturing an electronic component embedded substrate according to claim 30, wherein the forming a cavity comprises: forming a temporary remaining portion in a portion of the area in which the cavity is to be formed by processing a first temporary cavity having a “⊂”, shape and a second temporary cavity having a shape symmetrical to the first temporary cavity to face each other while being separated from each other by a predetermined interval; plating a conductive material on surfaces of the first temporary cavity and the second temporary cavity; and removing the temporary remaining portion. ### Claim 32 (depends on 30) The method of manufacturing an electronic component embedded substrate according to claim 30, wherein the forming a cavity comprises: forming a third temporary cavity in an area except a first projecting portion formed by projecting the insulating layer in the direction of a surface facing one surface of the cavity and a second projecting portion formed to be symmetrical to the first projecting portion on a surface facing the surface on which the first projecting portion is formed; plating a conductive material on a surface of the third temporary cavity; and removing portions of the first projecting portion and the second projecting portion. ### Claim 33 A method of manufacturing an electronic component embedded substrate, comprising: providing a first insulating layer having a first metal pattern on a lower surface and a second metal pattern on an upper surface; forming a cavity in the first insulating layer and forming a cavity plating portion electrically connected to at least one of the first metal pattern and the second metal pattern by plating a conductive material on a surface of the cavity; attaching a detach film to a lower surface of the first metal pattern; attaching a lower surface of an electronic component to the detach film by inserting at least a portion of the electronic component having a plurality of external electrodes on a surface; forming a conductive filling portion by filling a conductive material between the cavity plating portion and the external electrodes; forming a third insulating layer by applying an insulating material on exposed surfaces of the second metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component; forming a second insulating layer by applying an insulating material on the exposed surfaces of the first metal pattern, the first insulating layer, the cavity plating portion, the conductive filling portion, and the electronic component after removing a detach film; forming a first via passing through the second insulating layer and a first circuit pattern provided on a lower surface of the second insulating layer to be connected to the first via; and forming a third via passing through the third insulating layer and a second circuit pattern provided on an upper surface of the third insulating layer to be connected to the third via, wherein one surface of the first via is in contact with at least one area selected from at least a portion of the external electrodes, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the first metal pattern portion in contact with the cavity plating portion, and one surface of the third via is in contact with at least one area selected from at least a portion of the external electrodes, at least a portion of the conductive filling portion, at least a portion of the cavity plating portion, and at least a portion of the second metal pattern portion in contact with the cavity plating portion. ### Claim 34 (depends on 33) The method of manufacturing an electronic component embedded substrate according to claim 33, wherein the attaching a lower surface of an electronic component is performed to attach the lower surface of the electronic component to the detach film by inserting a plurality of electronic components in the cavity. ### Claim 35 (depends on 34) The method of manufacturing an electronic component embedded substrate according to claim 34, wherein at least two of the plurality of electronic components are connected in parallel.