Electrically programmable and eraseable memory device

A memory device comprising:

• a substrate;
• a tunneling layer over the substrate;
• a floating gate over the tunneling layer;
• a dielectric over the floating gate and comprising a first insulating layer over the floating gate, a second insulating layer over the first insulating layer, and a third insulating layer over the second insulating layer;
• and
• a control gate over the dielectric,
• wherein, the memory device is electrically erased by applying a positive voltage to the control gate and a drain while holding a source at ground and allowing the substrate to float, the positive voltage being of sufficient magnitude to eliminate a barrier presented by the second insulating layer, and to reduce a plurality of barriers presented by the first and third insulating layers,
• wherein the positive voltage provides a plurality of holes in the control gate with sufficient energy to overcome a valence energy level of the first and third insulating layers, and to cause the plurality of holes to travel through the first, second, and third insulating layers,
• further wherein, a conductive energy level of the second insulating layer is higher than a conductive energy level of the third insulating layer.