Low Voltage Register File Cell Structure
AssigneeApple Inc.
InventorsAjay Bhatia, Greg M. Hess, Sanjay P. Zambare
Life of this patent
Estimating the term…
Loading patent…
AssigneeApple Inc.
InventorsAjay Bhatia, Greg M. Hess, Sanjay P. Zambare
Estimating the term…
A register file cell structure to enable lower voltage writes is disclosed. In one embodiment, a register file includes a state element made up of two cross-coupled inverters. Each of the inverters includes a p-channel metal oxide semiconductor (PMOS) transistor having a source terminal coupled to a virtual voltage node. One or more PMOS transistors are coupled in series between the virtual voltage node and a global voltage node. Each of the one or more PMOS transistors includes a gate terminal that is hardwired to a ground node, and thus these devices remain active when power is applied to the global voltage node. The presence of the one or more PMOS devices coupled between the virtual and global voltage nodes results in the ability to overwrite contents stored in the state element at lower voltages than otherwise attainable without the one or more PMOS devices.
A register file comprising:
A register file bit cell comprising:
A circuit comprising:
A register file comprising:
An integrated circuit comprising:
Dependencies are inferred from the claim text.