High performance interconnect

An apparatus comprising

• a physical layer (PHY) configured to be coupled to a serial, differential link that is to include a number of lanes, the PHY to include a transmitter and a receiver to be coupled to each lane of the number of lanes, wherein the transmitter to be coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and wherein the PHY is to periodically issue a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration, wherein the PHY is to utilize the serial, differential link during the duration for a PHY associated task selected from a group consisting of an in-band reset, an entry into low power state, and an entry into partial width state.