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US 2014/0112089 A1Published application
Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid
AssigneeRambus Inc.
InventorsBrian Hing-Kit Tsang, Jared L. Zerbe
Life of this patent
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Abstract
Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.
Claims17
An integrated circuit (IC), comprising:
- a first node to output a clock signal having a clock signal frequency;
- a second node to output a data signal, wherein bits in the data signal are timed according to the clock signal;
- and
- circuitry to modify the clock signal frequency from a first frequency value to a second frequency value while the data signal is valid.
1 more element
A memory system, comprising:
- a memory controller;
- a memory device;
- a first signal line to couple a first set of pins on the memory controller with a first set of pins on the memory device, wherein the first signal line carries a clock signal having a clock signal frequency;
- a second signal line to couple a second set of pins on the memory controller with a second set of pins on the memory device, wherein the second line carries a data signal whose bits are timed according to the clock signal;
- wherein the memory controller includes circuitry to modify the clock signal frequency from a first frequency value to a second frequency value while the data signal is valid.
2 more elements
A method, comprising:
- transmitting a clock signal having a clock signal frequency;
- transmitting a data signal that is synchronous with respect to the clock signal;
- and
- modifying the clock signal frequency from a first frequency value to a second frequency value, wherein said modifying occurs while the data signal is valid, and wherein synchronicity between the clock signal and the data signal is maintained during said modifying.
1 more element
Dependencies are inferred from the claim text.