Refresh method, refresh address generator, volatile memory device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsChul-Woo PARK, Joo-Sun CHOI, Hong-Sun HWANG
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AssigneeSamsung Electronics Co., Ltd.
InventorsChul-Woo PARK, Joo-Sun CHOI, Hong-Sun HWANG
Estimating the term…
A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device.
A refresh method for a volatile memory device including a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns, each row corresponding to a respective address, the refresh method comprising:
The method of 4, wherein the counter-based refresh includes generating a refresh address at each increase of a counter value.
A refresh method for a volatile memory device including a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns, each row corresponding to a respective address, the refresh method comprising:
The method of 11, wherein the counter-based refresh includes generating a first refresh address at each increase of a counter value.
A method of performing a refresh operation in a memory device including a memory array having rows and columns, comprising:
Dependencies are inferred from the claim text.