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US 2014/0112085 A1Published application
Switched interface stacked-die memory architecture
AssigneeMicron Technology, Inc.
InventorsJoe M. Jeddeloh, Paul A. LaBerge
Life of this patent
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Abstract
Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
Claims20
An apparatus, comprising:
- a stacked-array memory vault configured such that no address associated with a contiguous area of defective memory cells on any die used to form the memory vault overlaps any address associated with a contiguous area of defective memory cells on any other die use to form the memory vault.
Dependencies are inferred from the claim text.