Data storage device, controller, and operating method of data storage device
AssigneeSamsung Electronics Co., Ltd.
InventorsWonseok LEE, Eun-Jin YUN, Youngkug MOON, Seongsik HWANG, Donghyun SOHN
Life of this patent
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Abstract
A nonvolatile memory is provided which includes a memory cell array including a plurality of nonvolatile memory cells; a decoder connected with the memory cell array through a plurality of word lines; a data input/output circuit connected with the memory cell array through a plurality of bit lines; a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal; and control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal.
Claims34
A nonvolatile memory comprising:
- a memory cell array including a plurality of nonvolatile memory cells;
- a decoder connected with the memory cell array through a plurality of word lines;
- a data input/output circuit connected with the memory cell array through a plurality of bit lines;
- a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal;
- and
- control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal.
A memory system comprising:
- a nonvolatile memory;
- and
- a memory controller configured to control the nonvolatile memory,
- wherein the nonvolatile memory includes,
- a memory cell array including a plurality of nonvolatile memory cells;
- a decoder connected with the memory cell array through a plurality of word lines;
- a data input/output circuit connected with the memory cell array through a plurality of bit lines;
- a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal;
- and
- control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal.
A memory system comprising:
- a nonvolatile main memory including a plurality of nonvolatile memory chips;
- and
- a memory controller configured to control the nonvolatile main memory,
- wherein the memory controller is configured to detect a variation in a power supply voltage and to control the nonvolatile main memory such that at least one nonvolatile memory chip of the plurality of nonvolatile memory chips is invalidated based on the detected variation.
An operating method of a nonvolatile memory which includes a plurality of nonvolatile memory cells, comprising:
- detecting a variation in a power supply voltage;
- and
- invalidating data stored at the plurality of nonvolatile memory cells in response to the detecting.
A computing system comprising:
- a nonvolatile main memory;
- a memory controller configured to control the nonvolatile main memory;
- and
- a central processing unit configured to access the nonvolatile main memory via the memory controller and to use the nonvolatile main memory as a working memory,
- wherein the nonvolatile main memory includes,
- a memory cell array including a plurality of nonvolatile memory cells,
- a decoder connected with the memory cell array through a plurality of word lines,
- a data input/output circuit connected with the memory cell array through a plurality of bit lines,
- a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal, and
- control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal.
A nonvolatile memory comprising:
- a memory cell array including a plurality of nonvolatile memory cells;
- a voltage detector configured to detect a variation in a power supply voltage being supplied to the nonvolatile memory and to output a voltage variation signal;
- and
- a controller configured to perform an overwriting operation on the memory cell array in response to the voltage variation signal, the overwriting operation causing data stored at the memory cell array to be overwritten with reset data.
Dependencies are inferred from the claim text.