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US 2014/0112068 A1Published application
Methods of programming memory devices
AssigneeMicro Technology, Inc.
InventorsAkira Goda, Andrew Bicksler, Violante Moschiano, Giuseppina Puzzilli
Life of this patent
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Abstract
Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage.
Claims20
A method of programming a memory device having a plurality of memory cells, the method comprising:
- biasing each data line of a plurality of data lines to a program inhibit voltage, wherein each data line of the plurality of data lines is coupled to one or more memory cells of the plurality of memory cells;
- discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming;
- and
- applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage.
1 more element
A method of programming a memory device having a plurality of memory cells, the method comprising:
- for a first portion of a programming operation:
- biasing a first portion of data lines of a plurality of data lines to a program enable voltage, wherein each data line of the plurality of data lines is coupled to one or more memory cells of the plurality of memory cells, and wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming for a first portion of a programming operation;
- biasing a second portion of data lines of the plurality of data lines to a first program inhibit voltage, wherein the second portion of data lines of the plurality of data lines are remaining data lines not coupled to the memory cells selected for programming for the first portion of the programming operation;
- and
- applying a plurality of first programming pulses to the memory cells selected for programming for the first portion of the programming operation while biasing the second portion of data lines of the plurality of data lines to the first program inhibit voltage;
- then
- for a second portion of the programming operation:
- biasing each data line of the plurality of data lines to a second program inhibit voltage;
- discharging a third portion of data lines of the plurality of data lines, wherein the third portion of data lines of the plurality of data lines are coupled to memory cells selected for programming for the second portion of the programming operation;
- and
- applying a plurality of second programming pulses to the memory cells selected for programming for the second portion of the programming operation while biasing a fourth portion of data lines of the plurality of data lines to the second program inhibit voltage, wherein the fourth portion of data lines of the plurality of data lines comprise data lines not coupled to the memory cells selected for programming for the second portion of the programming operation.
8 more elements
A method of programming a memory device having a plurality of memory cells, the method comprising:
- for a first portion of a programming operation:
- biasing each data line of a plurality of data lines to a first program inhibit voltage, wherein each data line of the plurality of data lines is coupled to one or more memory cells of the plurality of memory cells;
- discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming for the first portion of the programming operation;
- and
- applying a plurality of first programming pulses to the memory cells selected for programming for the first portion of the programming operation while biasing a second portion of data lines of the plurality of data lines to the first program inhibit voltage, wherein the second portion of data lines of the plurality of data lines are not coupled to memory cells selected for programming for the first portion of the programming operation;
- then
- for a second portion of the programming operation:
- biasing each data line of the plurality of data lines to a second program inhibit voltage;
- discharging a third portion of data lines of the plurality of data lines, wherein the third portion of data lines of the plurality of data lines are coupled to memory cells selected for programming for the second portion of the programming operation;
- and
- applying a plurality of second programming pulses to the memory cells selected for programming for the second portion of the programming operation while biasing a fourth portion of data lines of the plurality of data lines to the second program inhibit voltage, wherein the fourth portion of data lines of the plurality of data lines are not coupled to memory cells selected for programming for the second portion of the programming operation.
8 more elements
Dependencies are inferred from the claim text.