Sram global precharge, discharge, and sense

A design structure tangibly embodied in a machine-readable storage medium used in a design process of an SRAM, the design structure having elements that, when processed in a semiconductor manufacturing facility, produce an SRAM that comprises:

• a global bit line;
• an SRAM cell coupled to the global bit line to store one of a first logical value or a second logical value;
• precharge logic to precharge the global bit line to a precharge voltage for a non-read operation and to charge the global bit line to a boosted voltage that is greater than a reference voltage for a read operation;
• discharge logic for maintaining the global bit line at the boosted voltage for reading the first logical value stored on the SRAM cell and discharging the global bit line to a discharge voltage that is less than the reference voltage for reading the second logical value stored on the SRAM cell;
• and
• sense logic to output the first logical value when the global bit line is at the boosted voltage and to output the second logical value when the global bit line is at the discharge voltage.