Variable resistance nonvolatile memory device and method of writing thereby

A method for calculating an ON resistance of a selection circuit in a variable resistance nonvolatile memory device, the method comprising,

• where, in the variable resistance nonvolatile memory device having a k number of memory cell arrays commonly connected to a plurality of word lines and placed in order from a word line drive circuit, a wiring resistance of each of word lines in respective (k−1) blocks obtained by dividing the word lines by the k memory cell arrays is RWL, an ON resistance of a first selection circuit is R(1), and a current that flows through the selected memory cell has a first low resistance switching current IO, the first selection circuit connecting a write circuit and a selected memory cell that is a memory cell selected in a first memory cell array closest to the word line drive circuit, and the current flowing when the selected memory cell changes from a second resistance state to a first resistance state in which the selected memory cell has a resistance value less than a resistance value of the selected memory cell in the second resistance state,
• setting ON resistances of first to k-th selection circuits and causing first to k-th low resistance switching currents to be approximately equal to each other, by calculating, as a sum of voltage drops in the word lines in the respective blocks, a voltage drop VW(h) in the word lines between the word line drive circuit and an h-th (1≦h≦k) memory cell array, using at least a product of IO and RWL and a variable h, and by calculating an ON resistance R(h) of an h-th selection circuit that connects the write circuit and a memory cell selected in the h-th memory cell array, using at least IO, R(1), and VW(h), the first to k-th selection circuits respectively corresponding to first to k-th memory cell arrays, and the first to k-th low resistance switching currents respectively corresponding to the first to k-th memory cell arrays.

A variable resistance nonvolatile memory device comprising:

• a plurality of bit lines;
• a plurality of word lines and a plurality of source lines that cross the bit lines;
• a plurality of memory cells at cross points of the bit lines and the source lines, the memory cells each including a variable resistance element and a selection element whose ON-OFF control is performed by each of the word lines, and reversibly changing at least between a first resistance state and a second resistance state;
• a first write circuit that applies a write voltage to a first bit line that is at least one of the bit lines, where, among the memory cells, memory cells connected to the first bit line are grouped together as a first memory cell array;
• a second write circuit that applies a write voltage to a second bit line that is at least one of the bit lines and is different from the first bit line, where, among the memory cells, memory cells connected to the second bit line are grouped together as a second memory cell array;
• a first selection circuit that connects or disconnects at least one of the first write circuit and the first bit line;
• a second selection circuit that connects or disconnects at least one of the second write circuit and the second bit line;
• a first source line drive circuit that drives the source lines;
• and
• a word line drive circuit that selectively drives the word lines,
• wherein the memory cells include a memory cell for data storage and a memory cell not for data storage,
• the first write circuit and the second write circuit simultaneously apply the write voltage to the first bit line and the second bit line, respectively,
• memory cells to which the first write circuit and the second write circuit simultaneously write include the memory cell for data storage and the memory cell not for data storage that are on a same word line,
• the first memory cell array is placed closer to the first source line drive circuit than the second memory cell array is, and
• a first ON resistance is greater than a second ON resistance, the first ON resistance being a resistance value when a first selection element that is the selection element included in the first memory cell array is ON, and the second ON resistance being a resistance value when a second selection element that is the selection element included in the second memory cell array is ON.