US 2014/0112048 A1 · N-BIT ROM CELL

Abstract

Among other things, an n-bit ROM cell, such as a twin-bit ROM cell, and techniques for addressing one or more ROM cell portions of the n-bit ROM cell are provided. A twin-bit ROM cell comprises a first ROM cell portion adjacent to or substantially contiguous with a second ROM cell portion. The first ROM cell portion is associated with a first data bit value. The second ROM cell portion is associated with a second data bit value distinct from the first data bit value. Because the first ROM cell portion is adjacent to the second ROM cell portion, OD-to-OD spacing between the twin-bit ROM cell and an adjacent twin-bit ROM cell is increased to provide, for example, improved isolation, cell current, ROM speed, and VCCmin performance in comparison with single-bit ROM cells, while maintaining a substantially similar to pitch as the single-bit ROM cells.

Claims20

Dependent claims

A ROM cell array, comprising:

a ROM cell comprising a first ROM cell portion adjacent to a second ROM cell portion, the first ROM cell portion associated with a first data bit value and the second ROM cell portion associated with a second data bit value distinct from the first data bit value, the ROM cell configured according to a first coding scheme that maps one or more ROM codes to one or more bit lines.

A method for addressing a first ROM cell portion and a second ROM cell portion of a twin-bit ROM cell, comprising:

applying a first coding scheme to a twin-bit ROM cell, the applying a first coding scheme comprising:
responsive to a first ROM code being assigned to a first word line, associating the first word line with a first bit line based upon the first coding scheme mapping the first ROM code to the first bit line;
responsive to a second ROM code being assigned to a second word line, associating the second word line with a second bit line based upon the first coding scheme mapping the second ROM code to the second bit line;
responsive to a third ROM code being assigned to a third word line, associating the third word line with a third bit line based upon the first coding scheme mapping the third ROM code to the third bit line;
and
responsive to a fourth ROM code being assigned to a fourth word line, associating the fourth word line with a fourth bit line based upon the first coding scheme mapping the fourth ROM code to the fourth bit line.

3 more elements

Dependencies are inferred from the claim text.

N-bit rom cell

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N-bit rom cell

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Abstract

Claims20