US 2014/0112045 A1 · MEMORY SYSTEM INCORPORATING A CIRCUIT TO GENERATE A DELAY SIGNAL AND AN ASSOCIATED METHOD OF OPERATING A MEMORY SYSTEM

Abstract

Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells.

Claims25

Dependent claims

A memory system comprising:

a first memory array comprising a plurality of first memory cells,
each first memory cell requiring a corresponding time delay between wordline activating and bitline sensing during a read operation, and
said plurality of first memory cells requiring a range of different corresponding time delays between said wordline activating and said bitline sensing from long time delays corresponding to slow memory cells to short time delays corresponding to fast memory cells;
and
a delay signal generator receiving an input signal and delaying said input signal by a selected time delay within said long time delays so as to generate and output a delay signal.

2 more elements

A memory system comprising:

a first memory array comprising a plurality of first memory cells,
each first memory cell comprising at least one first transistor controlled by a first gate voltage,
each first memory cell requiring a corresponding time delay between wordline activating and bitline sensing during a read operation, and
said plurality of first memory cells requiring a range of different corresponding time delays between said wordline activating and said bitline sensing from long time delays corresponding to slow memory cells to short time delays corresponding to fast memory cells;
and
a delay signal generator receiving an input signal and delaying said input signal by a selected time delay within said long time delays so as to generate and output a delay signal, said delay signal generator comprising:
a second memory array comprising a plurality of second memory cells having a same design as said first memory cells such that said second memory cells similarly require said range of different corresponding time delays, said second memory cells each comprising at least one second transistor;
and
a reference voltage generator generating, for controlling said at least one second transistor, a second gate voltage that is less than said first gate voltage such that said input signal is delayed by said selected time delay.

6 more elements

A memory system comprising:

a first memory array comprising a plurality of first memory cells,
each first memory cell comprising at least one first transistor controlled by a first gate voltage,
each first memory cell requiring a corresponding time delay between wordline activating and bitline sensing during a read operation, and
said plurality of first memory cells requiring a range of different corresponding time delays between said wordline activating and said bitline sensing from long time delays corresponding to slow memory cells to short time delays corresponding to fast memory cells;
and
a delay signal generator receiving an input signal and delaying said input signal by a selected time delay within said long time delays so as to generate and output a delay signal, said delay signal generator comprising:
a second memory array comprising a plurality of second memory cells having a same design as said first memory cells such that said second memory cells similarly require said range of different corresponding time delays, said second memory cells each comprising at least one second transistor;
and
a variable reference voltage generator generating, for controlling said at least one second transistor, a selected one of multiple possible second gate voltages that are each less than said first gate voltage, said selected one of said multiple possible second gate voltages being preselected such that said input signal is delayed by said selected time delay.

6 more elements

A method of operating a memory system, said method comprising:

receiving, by a delay signal generator of said memory system, an input signal;
delaying, by said delay signal generator, said input signal by a selected time delay so as to generate a delay signal;
and
outputting, by said delay signal generator, said delay signal for timing of said memory system,
said memory system comprising a first memory array comprising a plurality of first memory cells, each first memory cell requiring a corresponding time delay between wordline activating and bitline sensing during a read operation, and said plurality of first memory cells requiring a range of different corresponding time delays between said wordline activating and said bitline sensing from long time delays corresponding to slow memory cells to short time delays corresponding to fast memory cells, and
said delaying being performed such that said selected time delay is within said long time delays corresponding to said slow memory cells.

3 more elements

Dependencies are inferred from the claim text.

Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system

Life of this patent

Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system

Life of this patent

Abstract

Claims25