Mosfet stack package
AssigneeNVIDIA Corporation
InventorShuang Xu
Life of this patent
Estimating the term…
Abstract
Embodiments of the invention provide methods and configuration for packaging multiple semiconductor ships in a semiconductor package. In one embodiment, an integrated circuit system includes a printed circuit board, a first MOSFET device disposed on a first surface of the printed circuit board, and a second MOSFET device disposed on a second surface of the printed circuit board, wherein the first MOSFET device overlaps an edge of the second MOSFET device in a direction extending through the printed circuit board.
Claims20
An integrated circuit system, comprising:
- a printed circuit board;
- a first MOSFET device disposed on a first surface of the printed circuit board;
- and
- a second MOSFET device disposed on a second surface of the printed circuit board, wherein the first MOSFET device overlaps an edge of the second MOSFET device in a direction extending through the printed circuit board.
The integrated circuit system, wherein the first MOSFET device is aligned in parallel to the second MOSFET device.
The integrated circuit system 1, wherein a source electrode pin of the first MOSFET device is configured to electrically connect to a source electrode pin of the second MOSFET device.
An integrated circuit system, comprising:
- a first MOSFET device disposed on a first surface of a printed circuit board;
- and
- a second MOSFET device electrically connected to the first MOSFET device through the printed circuit board, the second MOSFET device disposed on a second surface opposite the first surface of the printed circuit board, wherein the second MOSFET device is positioned at a location offset from a center of the first MOSFET device.
A method for manufacturing an integrated circuit system, comprising:
- providing a first MOSFET device electrically connected to a second MOSFET each disposed on opposite sides of a printed circuit board;
- and
- providing a third MOSFET device electrically connected to the second MOSFET disposed on an opposite where the second MOSFET is disposed, wherein the second MOSFET device is positioned at a location offset from a center of the first MOSFET device and the third MOSFET device is positioned at a location offset from a center of the second MOSFET device.
Dependencies are inferred from the claim text.