Bi-directional bipolar junction transistor for high voltage electrostatic discharge protection
AssigneeMacronix International Co., Ltd.
InventorsHsin-Liang Chen, Shuo-Lun Tu
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Abstract
A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.
Claims20
A bi-directional bipolar junction transistor (BJT) comprising:
- a p-type substrate;
- an N+ doped buried layer disposed adjacent to the substrate;
- a first P-type well region disposed adjacent to the N+ doped buried layer;
- a second P-type well region disposed adjacent to the N+ doped buried layer;
- an N-type well region adjacent to the N+ doped buried layer and encompassing the first and second P-type well regions such that at least a portion of the N-type well region is interposed between the first and second P-type well regions;
- first, second, and third field oxide (FOX) portions disposed adjacent to the N-type well region;
- and
- first, second, third, and fourth field plates, the first field plate being disposed adjacent to the first FOX portion, the second and third field plates being disposed adjacent to respective portions of the second FOX portion, and the fourth field plate being disposed adjacent to third FOX portion;
- wherein the first and second P-type wells each comprise at least one N+ doped plate and at least one P+ doped plate.
A circuit comprising a bi-directional high voltage electrostatic discharge (ESD) protection element, the bi-directional high voltage ESD protection element comprising:
- a p-type substrate;
- an N+ doped buried layer disposed adjacent to the substrate;
- a first P-type well region disposed adjacent to the N+ doped buried layer;
- a second P-type well region disposed adjacent to the N+ doped buried layer;
- an N-type well region adjacent to the N+ doped buried layer and encompassing the first and second P-type well regions such that at least a portion of the N-type well region is interposed between the first and second P-type well regions;
- first, second, and third field oxide (FOX) portions disposed adjacent to the N-type well region;
- and
- first, second, third, and fourth field plates, the first field plate being disposed adjacent to the first FOX portion, the second and third field plates being disposed adjacent to respective portions of the second FOX portion, and the fourth field plate being disposed adjacent to third FOX portion;
- wherein the first and second P-type wells each comprise at least one N+ doped plate and at least one P+ doped plate.
A semiconductor device comprising a first isolated high voltage n-channel metal oxide field effect transistor (HVNMOS) and a second isolated HVNMOS, wherein the first and second isolated HVNMOS are merged at a common N-type well isolation region.
Dependencies are inferred from the claim text.