Bi-directional bipolar junction transistor for high voltage electrostatic discharge protection
AssigneeMacronix International Co., Ltd.
InventorsHsin-Liang Chen, Shuo-Lun Tu
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Abstract
A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates.
Claims20
A bi-directional bipolar junction transistor (BJT) comprising:
- a p-type substrate;
- an N+ doped buried layer disposed adjacent to the substrate;
- a first P-type well region disposed adjacent to the N+ doped buried layer;
- a second P-type well region disposed adjacent to the N+ doped buried layer;
- and
- an N-type well region adjacent to the N+ doped buried layer and encompassing the first and second P-type well regions such that at least a portion of the N-type well region is interposed between the first and second P-type well regions;
- wherein the first and second P-type wells each comprise at least one N+ doped plate and at least one P+ doped plate.
A circuit comprising a bi-directional high voltage electrostatic discharge (ESD) protection element, the bi-directional high voltage ESD protection element comprising:
- a p-type substrate;
- an N+ doped buried layer disposed adjacent to the substrate;
- a first P-type well region disposed adjacent to the N+ doped buried layer;
- a second P-type well region disposed adjacent to the N+ doped buried layer;
- and
- an N-type well region adjacent to the N+ doped buried layer and encompassing the first and second P-type well regions such that at least a portion of the N-type well region is interposed between the first and second P-type well regions;
- wherein the first P-type well comprises first, second, and third N+ doped plates, first and second P+ doped plates, and first and second gate structures, the first P+ doped plate being disposed adjacent to the first N+ doped plate, the first gate structure being interposed between the first and second N+ doped plate, the second gate structure being interposed between the second and third N+ doped plate, and the second P+ doped plate being disposed adjacent to the third N+ doped plate;
- and
- further wherein the second P-type well comprises fourth, fifth, and sixth N+ doped plates, third and fourth P+ doped plates, and third and fourth gate structures, the third P+ doped plate being disposed adjacent to the fourth N+ doped plate, the third gate structure being interposed between the fourth and fifth N+ doped plate, the fourth gate structure being interposed between the fifth and sixth N+ doped plate, and the fourth P+ doped plate being disposed adjacent to the sixth N+ doped plate.
A semiconductor device comprising a first isolated low voltage n-channel metal oxide field effect transistor (LVNMOS) and a second isolated LVNMOS, wherein the first and second isolated LVNMOS share a common N-type well isolation region.
Dependencies are inferred from the claim text.