Drive circuit of liquid crystal panel

A drive circuit of liquid crystal panel, comprising a gate driver, a source driver, a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the data lines defining a plurality of pixel units, each of the pixel units comprising a thin-film transistor, a common electrode, a pixel electrode electrically connected to the thin-film transistor, and a storage capacitor, the thin-film transistor being electrically connected to the gate driver and the source driver respectively via the gate line and the data line, the common electrode and the pixel electrode constituting a liquid crystal capacitor, the storage capacitor being connected in parallel to the liquid crystal capacitor, the gate driver comprising a drive combination circuit, the drive combination circuit comprising a first electrical switch, an amplifier electrically connected to the first electrical switch, a first drive source of the amplifier electrically connected to the first electrical switch, a second drive source of the first electrical switch electrically connected to the amplifier, a first resistor electrically connected to two terminals of the amplifier, a third drive source electrically connected to the amplifier, a second resistor electrically connected to the first electrical switch, a second electrical switch electrically connected between the second resistor and the amplifier, a third resistor electrically connected to the amplifier, and a fourth drive source electrically connected to the second electrical switch;

• wherein the thin-film transistor comprises a gate terminal, a source terminal, and a drain terminal, the gate terminal being electrically connected via the gate line to the gate driver, the source terminal being electrically connected via the data line to the source driver, the drain terminal being electrically connected to the pixel electrode;
• wherein the first electrical switch comprises first, second, and third terminal, the first terminal being electrically connected to the first drive source, the second terminal being electrically connected to the second drive source and the amplifier, the third terminal being electrically connected to an end of the second resistor;
• wherein the second electrical switch comprises fourth, fifth, and the sixth terminal, the fourth terminal being electrically connected to an opposite end of the second resistor, the fifth terminal being electrically connected to the fourth drive source, the sixth terminal being electrically connected to the amplifier and an end of the first resistor;
• wherein the amplifier comprises seventh, eighth, and ninth terminals, the seventh terminal being electrically connected to the second drive source and the second terminal of the first electrical switch, the eighth terminal being electrically connected to the third drive source and an opposite end of the first resistor, the ninth terminal being electrically connected to the sixth terminal of the second electrical switch, an end of the first resistor, and the third resistor;
• wherein the gate terminal of the thin-film transistor is electrically connected to the end of the second resistor that is connected to the first electrical switch;
• wherein the first electrical switch is closed when the second terminal is controlled by a high level and is open by a low level, the second electrical switch being closed when the fifth terminal is controlled by a high level and is open by a low level;
• and
• wherein the first drive source provides a square wave, the second drive source providing a square wave having the same phase and period as those of the first drive source, the third drive source providing a triangular wave, the fourth drive source providing a square wave of a high frequency.