Solid-state imaging device, method for driving solid-state imaging device, and imaging device

A solid-state imaging device comprising:

• a pixel unit in which a plurality of unit pixels is arranged in rows and columns, the unit pixels performing photoelectric conversion of incident light to generate pixel information;
• and
• a memory unit in which a plurality of unit memories is arranged in rows and columns, the unit memories holding the pixel information,
• wherein each of the columns of the unit pixels includes the plurality of unit pixels in the column as a unit pixel block,
• the pixel unit includes:
• a pixel signal line disposed in each of the columns of the unit pixels;
• and
• a selection switch disposed between the unit pixel block and the pixel signal line, and shared by the plurality of unit pixels in the unit pixel block, and
• each of the unit memories includes a write transistor, a capacitor, and a read transistor.

A method for driving a solid-state imaging device,

• the solid-state imaging device including:
• a pixel unit in which a plurality of unit pixels is arranged in rows and columns, the unit pixels performing photoelectric conversion of incident light to generate pixel information;
• and
• a memory unit in which a plurality of unit memories is arranged in rows and columns, the unit memories holding the pixel information,
• each of the columns in the memory unit including, as a unit memory block, the unit memories in the column,
• the memory unit including:
• a memory signal line provided for each of the columns in the memory unit;
• and
• a selection switch provided between the unit memory block and the memory signal line, and shared by the plurality of unit memories in the unit memory block, and
• the memory signal line being shared by a plurality of columns of the unit memories,
• the method for driving the solid-state imaging device comprising
• turning ON different selection switches provided between the memory signal line and the unit memory block in a different column sharing the memory signal line, at different timing.