Gate driving circuit and method, and liquid crystal display

A liquid crystal display comprising a gate driving circuit comprising shift registers at a plurality of stages, wherein the shift register at each stage including a pull-up driving unit, a pull-up unit, a reset unit and a pull-down unit, said shift register further including:

• a supplementary unit;
• wherein,
• said pull-up unit is used for making a clock signal at a first clock terminal an output signal of the shift register at the present stage when being turned on;
• said supplementary unit, connected to said pull-up unit, is used for making a clock signal at a second clock terminal the output signal of the shift register at the present stage when being turned on.

A gate driving method for a gate driving circuit comprising shift registers at a plurality of stages, wherein the shift register at each stage including a pull-up driving unit, a pull-up unit, a reset unit and a pull-down unit, said shift register further including:

• a supplementary unit;
• wherein,
• said pull-up unit is used for making a clock signal at a first clock terminal an output signal of the shift register at the present stage when being turned on;
• said supplementary unit, connected to said pull-up unit, is used for making a clock signal at a second clock terminal the output signal of the shift register at the present stage when being turned on,
• the gate driving method comprising:
• turning on the pull-up driving unit and beginning to charge the shift register at the present stage when the output signal at the output terminal of the shift register at a previous stage is at a high level;
• turning on the pull-up unit and making the clock signal at the first clock terminal the output signal of the shift register at the present stage when the clock signal at the first clock terminal is at its high level and the clock signal at the second clock terminal is at a low level;
• the clock signal at said first clock terminal jumping into the low level, the clock signal at said second clock terminal jumping into its high level, turning on the supplementary unit and making the clock signal at said second clock terminal the output signal of the shift register at the present stage.