Shift Register Unit, Shift Register Circuit, Array Substrate And Display Device

A shift register unit comprising:

• a first pull-up unit connected with a high level end, a first clock signal end and a first control node (A);
• a first pull-down unit connected with a low level end, a second clock signal end, an input signal end, the first pull-up unit, a first output end and the first control node (A);
• a pull-down switch unit connected with the high level end, the low level end, the first clock signal end, the second clock signal end and a second control node (B);
• a second pull-down unit connected with the low level end, the second control node (B) and a second output end;
• and
• a second pull-up unit connected with the high level end, the first control node (A) and the second output end;
• wherein, the first pull-up unit is used to pull up a level of the first control node (A) when a low level is inputted into the first clock signal end;
• the first pull-down unit is used to pull down the level of the first control node (A) when a low level is inputted into both of the second clock signal end and the input signal end;
• the pull-down switch unit is used to pull down a level of the second control node (B) when a low level is inputted into the first clock signal end, and pull up the level of the second control node (B) when a low level is inputted into the second clock signal end;
• the second pull-up unit is used to pull up a level outputted from the second output end when the first control node (A) is at a low level, to output a driving signal;
• and the second pull-down unit is used to pull down the level outputted from the second output end when the second control node (B) is at a low level, to reset the driving signal.