Semiconductor device, method for manufacturing the semiconductor device, and method for controlling the semiconductor device

A semiconductor device comprising:

• a first semiconductor region of a first conductivity type;
• a second semiconductor region of a second conductivity type which is selectively provided in a surface layer of one side of the first semiconductor region;
• a third semiconductor region of the first conductivity type which is selectively provided inside the second semiconductor region;
• a trench which penetrates the second semiconductor region and the third semiconductor region and reaches the first semiconductor region;
• a gate insulating film which is provided inside the trench and along an inner wall of the trench;
• a gate electrode which is provided inside the trench and on an inner side of the gate insulating film;
• a fourth semiconductor region of the second conductivity type which is provided on another side of the first semiconductor region;
• a low life time region which is provided in an interface between the first semiconductor region and the fourth semiconductor region and which is shorter in carrier life time than any other region;
• a fifth semiconductor region of the second conductivity type which is provided in an outer circumferential portion of the first semiconductor region so as to extend from the one side of the first semiconductor region, penetrate the first semiconductor region and the low life time region and reach the fourth semiconductor region;
• a first electrode which touches the second semiconductor region and the third semiconductor region;
• and
• a second electrode which touches the fourth semiconductor region;
• wherein:
• the first semiconductor region is set to have a predetermined carrier life time by light ion irradiation to reduce the carrier life time.

A semiconductor device comprising:

• a first semiconductor element;
• a second semiconductor element which is electrically connected to an intermediate potential point between a high potential point and a low potential point of the first semiconductor element, the second semiconductor element including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type which is selectively provided in a surface layer of one side of the first semiconductor region, a third semiconductor region of the first conductivity type which is selectively provided inside the second semiconductor region, a gate electrode which is provided in a surface of a portion of the second semiconductor region which is located between the first semiconductor region and the third semiconductor region, agate insulating film being put between the gate electrode and the second semiconductor region, a fourth semiconductor region of the second conductivity type which is provided on another side of the first semiconductor region, a low life time region which is provided in an interface between the first semiconductor region and the fourth semiconductor region and which is shorter in carrier life time than any other region, a fifth semiconductor region of the second conductivity type which is provided in an outer circumferential portion of the first semiconductor region so as to extend from the one side of the first semiconductor region, penetrate the first semiconductor region and the low life time region and reach the fourth semiconductor region, a first electrode which touches the second semiconductor region and the third semiconductor region, and a second electrode which touches the fourth semiconductor region;
• and
• a control unit which controls the first semiconductor element and the second semiconductor element;
• wherein:
• the control unit turns on the first semiconductor element in order to bring the second semiconductor element into reverse recovery, and makes a variation of a current flowing in a turn-on state of the first semiconductor element smaller than 0.8 kA/μs.

A semiconductor device comprising:

• a first semiconductor element;
• a second semiconductor element which is electrically connected to an intermediate potential point between a high potential point and a low potential point of the first semiconductor element, the second semiconductor element including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type which is selectively provided in a surface layer of one side of the first semiconductor region, a third semiconductor region of the first conductivity type which is selectively provided inside the second semiconductor region, a trench which penetrates the second semiconductor region and the third semiconductor region and reaches the first semiconductor region, a gate insulating film which is provided inside the trench and along an inner wall of the trench, a gate electrode which is provided inside the trench and on an inner side of the gate insulating film, a fourth semiconductor region of the second conductivity type which is provided on another side of the first semiconductor region, a low life time region which is provided in an interface between the first semiconductor region and the fourth semiconductor region and which is shorter in carrier life time than any other region, a fifth semiconductor region of the second conductivity type which is provided in an outer circumferential portion of the first semiconductor region so as to extend from the one side of the first semiconductor region, penetrate the first semiconductor region and the low life time region and reach the fourth semiconductor region, a first electrode which touches the second semiconductor region and the third semiconductor region, and a second electrode which touches the fourth semiconductor region;
• and
• a control unit which controls the first semiconductor element and the second semiconductor element;
• wherein:
• the control unit turns on the first semiconductor element in order to bring the second semiconductor element into reverse recovery, and makes a variation of a current flowing in a turn-on state of the first semiconductor element smaller than 0.8 kA/μs.

A method for manufacturing a semiconductor device including a first conductivity type semiconductor region, a metal/oxide film/semiconductor insulating gate structure which is provided on one side of the first conductivity type semiconductor region, a first second conductivity type semiconductor region which is provided on another side of the first conductivity type semiconductor region, a low life time region which is provided in an interface between the first conductivity type semiconductor region and the first second conductivity type semiconductor region and which is shorter in carrier life time than any other region, a second second conductivity type semiconductor region which is provided in an outer circumferential portion of the first conductivity type semiconductor region so as to extend from the one side of the first conductivity type semiconductor region, penetrate the first conductivity type semiconductor region and the low life time region and reach the first second conductivity type semiconductor region, and an output electrode which touches the first second conductivity type semiconductor region, the method for manufacturing the semiconductor device comprising:

• a first step of selectively forming the second second conductivity type semiconductor region in the outer circumferential portion of the first conductivity type semiconductor region at a determined depth from one main surface of the first conductivity type semiconductor region;
• a second step of forming the insulating gate structure on the one main surface side of the first conductivity type semiconductor region after the first step;
• a third step of carrying out light ion irradiation to reduce a carrier life time so as to set the first conductivity type semiconductor region at a predetermined carrier life time after the second step;
• and
• a fourth step of forming the first second conductivity type semiconductor region on the other main surface of the first conductivity type semiconductor region after the third step so that the first second conductivity type semiconductor region can touch the second second conductivity type semiconductor region.

A method for controlling a semiconductor device including a first semiconductor element and a second semiconductor element which is electrically connected to an intermediate potential point between a high potential point and a low potential point of the first semiconductor element, the second semiconductor element including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type which is selectively provided in a surface layer of one side of the first semiconductor region, a third semiconductor region of the first conductivity type which is selectively provided inside the second semiconductor region, a gate electrode which is provided in a surface of a portion of the second semiconductor region which is located between the first semiconductor region and the third semiconductor region, a gate insulating film being put between the gate electrode and the second semiconductor region, a fourth semiconductor region of the second conductivity type which is provided on another side of the first semiconductor region, a lowlife time region which is provided in an interface between the first semiconductor region and the fourth semiconductor region and which is shorter in carrier life time than any other region, a fifth semiconductor region of the second conductivity type which is provided in an outer circumferential portion of the first semiconductor region so as to extend from the one side of the first semiconductor region, penetrate the first semiconductor region and the lowlife time region and reach the fourth semiconductor region, a first electrode which touches the second semiconductor region and the third semiconductor region, and a second electrode which touches the fourth semiconductor region, the method for controlling the semiconductor device comprising the step of:

• turning on the first semiconductor element in order to bring the second semiconductor element into reverse recovery, and making a variation of a current flowing in a turn-on state of the first semiconductor element smaller than 0.8 kA/μs.

A method for controlling a semiconductor device including a first semiconductor element and a second semiconductor element which is electrically connected to an intermediate potential point between a high potential point and a low potential point of the first semiconductor element, the second semiconductor element including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type which is selectively provided in a surface layer of one side of the first semiconductor region, a third semiconductor region of the first conductivity type which is selectively provided inside the second semiconductor region, a trench which penetrates the second semiconductor region and the third semiconductor region and reaches the first semiconductor region, a gate insulating film which is provided inside the trench and along an inner wall of the trench, a gate electrode which is provided inside the trench and on an inner side of the gate insulating film, a fourth semiconductor region of the second conductivity type which is provided on another side of the first semiconductor region, a low life time region which is provided in an interface between the first semiconductor region and the fourth semiconductor region and which is shorter in carrier life time than any other region, a fifth semiconductor region of the second conductivity type which is provided in an outer circumferential portion of the first semiconductor region so as to extend from the one side of the first semiconductor region, penetrate the first semiconductor region and the lowlife time region and reach the fourth semiconductor region, a first electrode which touches the second semiconductor region and the third semiconductor region, and a second electrode which touches the fourth semiconductor region, the method for controlling the semiconductor device comprising the step of:

• turning on the first semiconductor element in order to bring the second semiconductor element into reverse recovery, and making a variation of a current flowing in a turn-on state of the first semiconductor element smaller than 0.8 kA/μs.

A device, comprising:

• a substrate region of a first conductivity type, and having irradiated carriers;
• at least two regions of a second conductivity type formed in a surface of the substrate region;
• an emitter region formed in each of the at least two regions of the second conductivity type;
• a contact region formed in each of the at least two regions of the second conductivity type;
• a collector region formed on an opposite surface of the substrate region;
• an interface region formed between the collector region and the substrate region, the interface region having carriers with lifetimes shorter than in any of other regions of the device;
• an electrode in contact with each emitter region and each contact region;
• and
• an electrode in contact with the collector region.