Frequency divider, clock generating apparatus, and method capable of calibrating frequency drift of oscillator
AssigneeMediatek Inc.
InventorsYu-Ming Ying, Shiue-Shin Liu
Life of this patent
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Abstract
A clock generating apparatus includes an oscillator and a frequency synthesizer. The oscillator is utilized for generating a reference clock signal. The frequency synthesizer is coupled to the oscillator and utilized for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.
Claims19
A clock generating apparatus, comprising:
- an oscillator, for generating a reference clock signal;
- and
- a frequency synthesizer, coupled to the oscillator, for synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated, and outputting the target clock signal as an output of the clock generating apparatus.
A method used for a clock generating apparatus, comprising:
- providing an oscillator for generating a reference clock signal;
- synthesizing a target clock signal in accordance with the reference clock signal and a frequency division factor that has been adjusted or compensated;
- and
- outputting the target clock signal as an output of the clock generating apparatus.
A clock generating apparatus, comprising:
- an oscillator, for generating a reference clock signal;
- and
- a phase control circuit, coupled to the oscillator, for selecting at least two phase shifts from different phase characteristics that are generated based on the reference clock signal, and interpolating a phase shift according to the selected phase shifts, so as to generate a target clock signal.
A fractional divider, comprises:
- a phase selector, for selecting at least two phase shifts from different phase characteristics that are generated based on a reference clock signal provided by an oscillator;
- a phase interpolator, coupled to the phase selector, for interpolating a phase shift according to the selected phase shifts, so as to generate a target clock signal having a frequency that is a frequency of the reference clock signal divided by a frequency division factor;
- and
- a sigma-delta modulator (SDM), coupled to the phase selector and the phase interpolator, for respectively controlling the phase selector and the phase interpolator to calibrate the frequency of the target clock signal by adjusting/compensating the frequency division factor.
Dependencies are inferred from the claim text.