Deserializers

A deserializer comprising:

• an internal clock generator configured to divide a data strobe signal and a complementary data strobe signal to generate internal clock signals;
• a data aligner configured to align data in response to the internal clock signals to generate higher aligned data and lower aligned data;
• a phase detection signal generator configured to generate a phase detection signal including a pulse generated according to a write command signal and a write latency signal;
• a selection signal generator configured to detect a phase of one of the internal clock signals in response to the phase detection signal to generate a selection signal;
• and
• a selection output unit configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.

A deserializer comprising:

• a selection signal generator configured to detect a phase of one of an internal clock signals in response to a phase detection signal including a pulse generated according to a write command signal and a write latency signal to generate a selection signal;
• a clock phase controller configured to output the internal clock signals or inversed signals of the internal clock signals as transformed clock signals in response to the selection signal;
• and
• a data aligner configured to align data in response to the transformed clock signals to generate aligned data.

A deserializer comprising:

• an internal clock generator configured to divide a data strobe signal and a complementary data strobe signal to generate internal clock signals;
• a phase detection signal generator configured to generate a phase detection signal including a pulse generated according to a write command signal and a write latency signal;
• a selection signal generator configured to detect a phase of one of the internal clock signals in response to the phase detection signal to generate a selection signal;
• a clock phase controller configured to output the internal clock signals or inversed signals of the internal clock signals as transformed clock signals in response to the selection signal;
• and
• a data aligner configured to align data in response to the transformed clock signals to generate aligned data.

A deserializer comprising:

• a selection signal generator configured to detect a phase of one of an internal clock signals in response to a phase detection signal including a first pulse generated according to a write command signal and a write latency to generate a selection signal;
• a first selector configured to output a first alignment data group or a second alignment data group as a first selected alignment data group in response to the selection signal;
• and
• a second selector configured to output the first alignment data group or the second alignment data group as a second selected alignment data group in response to the selection signal.

A deserializer comprising:

• a phase controller configured to generate a phase detection signal, a first data input clock signal and a second data input clock signal including respective ones of a first pulse, a second pulse and a third pulse which are created according to a write command signal and a write latency;
• a data selector configured to output a first alignment data group or a second alignment data group as a first selected alignment data group in response to a selection signal and output the first alignment data group or the second alignment data group as a second selected alignment data group in response to the selection signal, the selection signal being generated by detecting a phase of one of first to fourth internal clock signals in response to the phase detection signal;
• and
• an internal data generator configured to latch the first selected alignment data group in response to the first data input clock signal to generate a first internal data group and latch the second selected alignment data group in response to the second data input clock signal to generate a second internal data group.

A method of deserializing, comprising:

• aligning data in response to internal clock signals having different phases from each other for generating higher aligned data and lower aligned data;
• detecting a phase of one of the first to fourth internal clock signals in response to a phase detection signal including a pulse generated according to a write command signal and a write latency signal to generate a selection signal;
• and
• outputting the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.