Methods and apparatus for building bus interconnection networks using programmable interconnection resources

An integrated circuit, comprising:

• a logic region having a plurality of registers operable to provide logic region output signals;
• a first interconnect;
• a second interconnect;
• a bypass path coupled to the first interconnect, wherein the bypass path propagates a bypass signal;
• and
• output selection and routing circuitry coupled to the second interconnect, wherein the output selection and routing circuitry receives each of the logic region output signals and the bypass signal and wherein the output selection and routing circuitry further routes a selected one of the bypass signal and the logic region output signals to the second interconnect.

A method for operating an integrated circuit comprising:

• producing a plurality of data signals in a first logic region in a plurality of logic regions;
• generating a destination address in the first logic region in the plurality of logic regions, wherein the destination address is associated with a destination logic region in the plurality of logic regions;
• and
• transmitting the plurality of data signals and the destination address via a selected subset of the plurality of interconnects, wherein the selected subset of the plurality of interconnects is interposed between the first logic region in the plurality of logic regions and a second logic region in the plurality of logic regions.