Localized printed circuit board layer extender apparatus for relieving layer congestion near high pin-count devices
AssigneeQUALCOMM Incorporated
InventorsJames L. Blair, John A. Kolano
Life of this patent
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Abstract
A method and apparatus for a localized printed circuit board layer extender (LLX) is provided. The apparatus relieves layer routing congestion in and around high pin count integrated circuits. The method begins when a localized layer extender is provided that is compatible with the bottom-side pin-field of a device under test (DUT). The LLX is affixed to the bottom-side pin-field of the DUT. Test signals are then routed through the LLX as part of a test procedure. The apparatus includes: a LLX that substantially matches the pin-field of a bottom side of a DUT; a LLX base; and a LLX debug interface.
Claims22
A method for testing an electronic device, comprising:
- providing a localized layer extender (LLX) compatible with a bottom-side pin-field of a device under test (DUT);
- affixing the LLX to the bottom-side pin-field of the DUT;
- and
- routing signals through the LLX as part of a test procedure.
An apparatus for testing an electronic device, comprising:
- a localized layer extender (LLX) board substantially matching a pin-field of a bottom-side of a device under test (DUT);
- a LLX base;
- a LLX top electrical component mounting surface;
- a LLX electrical interface;
- and
- a LLX debug interface.
An apparatus for testing an electronic device, comprising:
- means for providing a localized layer extender (LLX) compatible with a bottom-side pin-field of a device under test (DUT);
- means for affixing the LLX to the bottom side pin-field of the DUT;
- and
- means for routing signals through the LLX as part of a test procedure.
Dependencies are inferred from the claim text.