Reference voltage generation circuit
AssigneeLapis Semiconductor Co., Ltd.
InventorAkira AKAHORI
Life of this patent
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Abstract
A reference voltage generation circuit includes a standard electrical current path including at least a pair of NMOS and PMOS, and a constant electrical current supplying circuit for supplying a constant electrical current to the standard electrical current path. The pair of NMOS and PMOS is configured to share a gate potential and a source-drain electrical current. Accordingly, the reference voltage generation circuit is configured to generate a reference voltage as a potential difference between two positions sandwiching the NMOS and PMOS. The reference voltage generation circuit further includes a timing compensation circuit. The timing compensation circuit includes a compensation DMOS for forming a detour electrical current path for bypassing the NMOS according to an on signal.
Claims8
A reference voltage generation circuit, comprising:
- a standard electrical current path including at least a pair of NMOS (an enhancement type NMOS field effect transistor) and PMOS (an enhancement type PMOS field effect transistor);
- a constant electrical current supplying circuit for supplying a constant electrical current to the standard electrical current path;
- and
- a timing compensation circuit,
- wherein said NMOS and PMOS share a gate potential and a source-drain electrical current so that the reference voltage generation circuit generates a reference voltage as a potential difference between two positions sandwiching the NMOS and PMOS, and
- said timing compensation circuit includes a compensation DMOS (a depletion type NMOS field effect transistor) for forming a detour electrical current path for bypassing the NMOS according to an on signal.
Dependencies are inferred from the claim text.