Chip arrangement and a method for forming a chip arrangement

A method for forming a chip arrangement, the method comprising:

• electrically connecting a first chip to a first chip carrier top side, wherein the first chip carrier comprises a first chip carrier top side and a first chip carrier bottom side;
• electrically connecting a second chip to a second chip carrier top side, wherein the second chip carrier comprises a second chip carrier top side and a second chip carrier bottom side;
• at least partially surrounding the first chip carrier and the second chip carrier with an electrically insulating material;
• forming at least one electrical interconnect to electrically contact the first chip to the second chip through the electrically insulating material;
• forming one or more first electrically conductive portions and one or more second electrically conductive portions over the electrically insulating material,
• wherein forming one or more first electrically conductive portions and one or more second electrically conductive portions over the electrically insulating material comprises
• forming the one or more first electrically conductive portions over and electrically contacting the one or more first electrically conductive portions to at least one of the first chip carrier top side and second chip carrier top side, and
• forming the one or more second electrically conductive portions over and electrically contacting the one or more first electrically conductive portions to at least one of the first chip carrier bottom side and second chip carrier bottom side.